臺灣博碩士論文加值系統

在這本論文中，展示兩個V頻段的功率放大器及線性器，還有一個X頻段的大功率放大器的設計與量測成果，其中前兩個V頻段放大器使用的是台積電40奈米的CMOS製程，另一個X頻段的放大器則是使用穩懋250奈米的氮化鎵(GaN)高速場效電晶體( HEMT)製程設計。
首先是應用於深耕計畫的60-GHz線性放大器，其規格要求主要是希望在功耗80 mW的情況下OP1dB能達到8 dB以上的輸出功率，因此此電路使用共源極 (Common source)架構，並使用變壓器來減少損耗、縮小面積、利用變壓器的高轉阻比特性使電路更好匹配等特性來達到輸出功率的合併，最後利用預失真 (Pre-distortion)的技巧，用增益換取OP1dB的改善，此電路設計過程中使用負轉導 (-gm)原件調整增益幅度，用並聯閘級端電容調整頻飄，如此可以使電路的量測與模擬相符，並在60 GHz達到11.8-dBm的PSAT、7.4-dBm的OP1dB、和23.8 dB的增益，另外如果將預失真 (Pre-distortion)電路中的偏壓從0.7 V調整為0.6 V，其會使增益下降但OP1dB會改善1.1 dB。
接著介紹60-GHz的功率放大器，其主要是希望增益能大於20 dB、飽合輸出功率大於20 dBm、效率大於20%，因此使用了共源極 (Common source)架構、8路的變壓器 (Transformer)功率合併以達到高輸出功率，並使用中和(Neutralization)電容的技巧提高增益和穩定度。此電路的模擬與量測結果相差不大，最後在60 GHz達到19.8 dBm的PSAT、18.3%的PAE，以及在54.5 GHz達到最高25.5 dB的增益，另外從51到62.4 GHz有11.4 GHz的3-dB增益頻寬。
最後則是10-GHz的大功率放大器，此放大器希望使用較簡單的架構來驗證穩懋的先進製程250-nm GaN HEMT，因此使用共源極 (Common source)架構維持線性度、2路的功率合併增加輸出功率、2級的放大器增加增益，並使用最簡單的傳輸線進行匹配，最後則是使用散熱PCB版的設計改善溫度過高的問題，使量測不會因為熱效應導致與模擬結果相差太多的情況發生，最後量測結果在10 GHz達到31 dBm的PSAT、28.9 dBm的OP1dB，以及在7.7 GHz達到最高20.6 dB的增益、另外從7到9 GHz有2 GHz的3-dB增益頻寬。

This thesis demonstrates the design and measurement results of three amplifiers which are V-band high linearity amplifier and power amplifier in 40-nm CMOS process and X-band high power amplifier in 250-nm GaN HEMT process.
The first part is a 60-GHz high linearity amplifier (HLA) with low power consump-tion. This design adopted the common source configuration to increase the linearity. The transformers are adopted to reduce the loss, size and increase the efficiency. The pre-distortion technique is also used to reduce gain expansion characteristic to compen-sate the gain compression of the PA. It can improve the OP1dB and linearity. This HLA achieves the measured saturated output power (PSAT) of 11.8 dBm, output 1-dB com-pression point (OP1dB) of 7.4 dBm, and 23.8-dB small signal gain with 11.4% peak power-added efficiencies (PAE) at 60 GHz. The pre-distortion circuit improves 1.1 dB of OP1dB at 60 GHz by revising the gate bias from 0.7 V to 0.6 V.
The next is a V-band transformer-based power amplifier (PA). It is a three-stage PA with eight-way transformer combining at output stage. This PA uses the transformers with dc path of metal-one and neutralization technique to improve the passive loss and asymmetric problem, as well as the gain and stability. This PA achieves the measured saturated output power (PSAT) of 19.8 dBm with 18.3% peak power-added efficiencies (PAE) at 60 GHz. The peak gain is 25.5 dB at 54.5 GHz with a 3-dB bandwidth of 11.4 GHz from 51 to 62.4 GHz.
The last part is a 10-GHz high power amplifier. It realizes in a simple architecture to verify the process of GaN HEMT. The common source configuration is used to maintain linearity. Two way output combining is adopted to increase the output power. Two stage design is adopted to increase the gain performance as well. In addition, the thermal problem should be resolved in high output power, and some cooling techniques are pre-sented in this design. This HPA achieves a measured PSAT of 31 dBm with 10.6% peak PAE at 10 GHz. The measured peak gain is 20.6 dB at 7.7 GHz with a 3-dB band-width of 2 GHz from 7 to 9 GHz.

CONTENTS
誌謝 ii
中文摘要 iv
ABSTRACT vi
CONTENTS viii
LIST OF FIGURES xi
LIST OF TABLES xvii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Literature Survey 3
1.2.1 The V-band Power Amplifiers for Linearity 3
1.2.2 The V-band Power Amplifiers for Large Power and Efficiency 5
1.2.3 The X-band High Power Amplifiers 7
1.3 Contributions 9
1.4 Thesis Organization 10
Chapter 2 The V-band High Linearity Amplifier in 40-nm CMOS for Application of Transmitter 11
2.1 Introduction 11
2.1.1 Project Overview and Circuit Specification 11
2.1.2 The Linearization of Pre-distortion Technique 13
2.2 Circuit Design 14
2.2.1 Circuit Architecture 14
2.2.2 Device Selections 15
2.2.3 Circuit Design 19
2.2.4 Circuit Schematics 29
2.3 Simulation Results and Layout 31
2.4 Experimental Results 40
2.5 Discussion 43
2.6 Summary 44
Chapter 3 The V-band 40-nm CMOS Power Amplifier with Transformer and Neutralization Technique for High-Power and High-Efficiency 46
3.1 Introduction 46
3.1.1 Power Combining Techniques for MMW Power Amplifiers [21] 46
3.1.2 Transformer-Based Power Amplifiers Combining 48
3.2 V-band High-Power High-Efficiency Power Amplifiers Circuit Design 49
3.2.1 Circuit Architecture 49
3.2.2 Device Selections 51
3.2.3 Circuit Design 55
3.2.4 Circuit Schematics 62
3.3 Simulation Results and Layout 64
3.4 Experiment Results and Discussion 71
3.5 Summary 74
Chapter 4 The X-band Power Amplifiers in 250-nm GaN HEMT with Cooling Technique 76
4.1 Introduction 76
4.1.1 The Cooling Methods of Chip in High Power Level 76
4.2 X-band Power Amplifiers Circuit Design 77
4.2.1 Circuit Architecture 77
4.2.2 Device Selections 78
4.2.3 Circuit Design 81
4.2.4 Circuit Schematics 84
4.3 Simulation Results and Layout 86
4.4 Experiment results 92
4.5 Discussions 94
4.5.1 The Thermal Problem on the Chip 94
4.5.2 Cooling Technique 95
4.5.3 Re-Simulation 97
4.6 Summary 99
Chapter 5 Conclusions 101
References 103

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