臺灣博碩士論文加值系統

現今的異質系統架構提供快取一致性互連連接中央處理器與通用圖形處理器，藉此提供低延遲以及低耗能的晶片內部資料傳輸。然而傳統的中央處理器與通用圖形處理器的執行模式並無法有效率的使用快取一致性互連，原因是傳統的執行模式會讓中央處理器先將資料準備完成，再呼叫通用圖形處理器開始執行。這樣的方式會讓通用圖形處理器開始執行時中央處理器所準備的資料都溢出到外部的記憶體。本碩論中，我們出新的中央處理器與通用圖形處理器的共同執行模式讓中央處理器準備資料的同時通用圖形處理器能夠一邊執行準備好的資料，藉此減少準備的資料溢出到外部的記憶體，而能夠更有效的利用快取一致性互連。藉由新提出的應用程式介面，我們能夠用更小的細粒度控制中央處理器準備資料以及通用圖形處理器的執行，讓準備的資料能夠從中央處理器的快取透過快取一致性互連傳到通用圖形處理器的快取。實驗結果顯示，我們提出的中央處理器與通用圖形處理器的共同執行模式相較於傳統的執行模式能夠有效降低 64% 外部記憶體存取，改善11% 通用圖形處理器效能，以及 58% 整體執行時間。

Modern HSAs support the cache coherent interconnect between CPU and GPU to provide low latency and energy-efficient on-chip data movement. However, the coventional CPU-GPU execution model incurs inefficient usage of the cache coherent interconnect since separation of CPU data preparation and GPU kernel execution can result in large data eviction. In this paper, we propose a coordinated CPU-GPU execution model that enables CPU to prepare data in finer granularity while GPU executes kernel at the same time to better utilize the coherent interconnect. With new APIs, we are allowed to control data preparation and kernel execution such that data can be fine-grainedly transferred from CPU to GPU cache. Evaluations show that, on average, the proposed scheme saves 64% external memory accesses, improves GPU kernel time by 11% and total execution time by 58% over the conventional one.

致謝 i
摘要 ii
Abstract iii
1 Introduction 1
2 Background & Motivation 3
2.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Integraed CPU-GPU Architecture . . . . . . . . . . . . . . . . . 3
2.1.2 GPGPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Coordinated CPU-GPU Execution 7
3.1 Fine-Grained Data Preparing & Signaling Mechanism . . . . . . . . . . . 8
3.2 Throttling Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Microarchitecture Extension . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Compiler and Runtime Support . . . . . . . . . . . . . . . . . . . . . . . 12
4 Evaluation 15
4.1 Methodalogy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.1 GPU kernel time improvement . . . . . . . . . . . . . . . . . . . 16
4.2.2 Effect of throttling mechanism . . . . . . . . . . . . . . . . . . . 16
4.2.3 Effect of workloads with short kernel time . . . . . . . . . . . . . 18
4.2.4 Total execution time improvement . . . . . . . . . . . . . . . . . 19
5 Related Works 21
5.1 Reduce coherence overhead in multiprocessor . . . . . . . . . . . . . . . 21
5.2 Heterogeneous system coherence for integrated CPU-GPU systems . . . . 22
5.3 CPU prefetches data for GPU . . . . . . . . . . . . . . . . . . . . . . . . 22
6 Conclusion 23
Bibliography 24

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