臺灣博碩士論文加值系統

在顯示科技方面上，金屬氧化物半導體因擁有較高的均勻度利於大面積製程、可低溫製程、較低的製程費用等優點，因此被視為現今最具潛力的薄膜電晶體材料。場效載子遷移率扮演影響薄膜電晶體電特性好壞一很重要的腳色，對金屬氧化物來說，影響其內部載子遷移率有兩大因素，第一個為金屬氧化物內載子的濃度，這項因素我們能藉由採用high-k閘極絕緣層材料來做改善，第二個則是其內部缺陷密度，就這部分而言，我們通常會改變沉積時不同氣體的通量，來降低此情況的發生。然而本論文將利用有別於舊有改善做法的方式，來降低元件內部之缺陷密度，我們提出的概念為運用isotype homojunction會形成能障的特點，使通道層形成在離閘極絕緣層較遠處，如此一來可避免通道層受到閘極絕緣層和主動層間界面缺陷的影響，而達到較佳電特性的薄膜電晶體。改善過後的場效載子遷移率可達44.73 cm2/Vs，約為對照組的兩倍，缺陷密度指標的次臨界斜率也有明顯的提升。

Amorphous oxide semiconductors (AOSs) represented by amorphous indium-gallium-zinc oxide (a-IGZO) are considered to be the most competitive materials in display industry for its great uniformity over large size display, low fabrication temperature and low production cost. Field effect mobility plays a crucial role in the quest to achieve high performance thin film transistor (TFT) using oxide semiconductor as its active layer. Two main factors that contribute to field effect mobility of oxide TFT are carrier concentration and trap densities. The former can be improved through the implementation of high k dielectric. As for the latter, it is typically reduced by tuning the deposition condition. However, instead of minimizing trap densities by controlling film deposition condition, I have developed a novel approach which deposits an extremely high oxygen partial pressure amorphous indium-gallium-zinc oxide layer prior to the active layer, followed by distinct dual thermal annealing process. By adopting the proposed idea, it is possible to form a channel layer at the interface of high oxygen partial pressure a-IGZO layer and active layer due to isotype homojunction concept. This means that the channel will not be affected by the interface traps created through atomic disruption of different materials. As a result, the field effect mobility of my device can be enhanced to 44.73 cm2/Vs, which represents a two times improvement in the field effect mobility as compared to the control sample. An explicit reduction on subthreshold swing, an indicator of trap densities, can also be observed.

目錄
論文摘要 I
Abstract II
誌謝 III
目錄 IV
表目錄 VIII
圖目錄 IX
Chapter 1 概論 1
1.1 研究背景 1
1.2 研究動機與方向 3
1.3 論文大綱 4
Chapter 2 材料介紹與理論基礎 5
2.1 閘極絕緣層高介電材料 5
2.1.1 元件尺寸的發展 5
2.1.2 高介電材料的興起 6
2.1.3 高介電材料的選擇 7
2.1.4 常見的高介電材料的種類 10
2.1.5 高介電材料HfO2之製程方式 10
2.2 金屬氧化物半導體介紹 11
2.2.1 金屬氧化物半導體材料概述 11
2.2.2 非晶氧化銦鎵鋅材料特性 11
2.3 非晶金屬氧化物半導體傳輸機制與其能隙間的電子組態 14
2.4 金屬氧化物薄膜電晶體結構 16
2.5 金屬氧化物薄膜電晶體之製程開發 18
2.5.1 脈衝雷射法 (Pulsed laser deposition, PLD) 18
2.5.2 浸沾法 (Sol-gel) 18
2.5.3 旋轉塗佈 ( Spin coating ) 19
2.5.4 濺鍍法 ( Sputter ) 19
2.6 金屬氧化物膜電晶體操作模式 19
2.7 TFT元件參數萃取方式 22
2.7.1 載子遷移率(Mobility, μ) 23
2.7.2 臨界電壓 (Threshold Voltage, Vth) 25
2.7.3 次臨界斜率 (Subthreshold Swing, S.S.) 26
2.7.4 開關電流比(On/Off Current Ratio, IOn/IOff) 26
2.7.5 半導體參數分析儀 (Semiconductor Parameter Analyzer) 27
2.8 a-IGZO薄膜材料分析 27
2.8.1 場發射掃描式電子顯微鏡 (FE-SEM) 27
2.8.2 四點探針(Four Point Probes) 28
2.8.3 霍爾量測(Hall Effect Measurement) 29
Chapter 3 使用雙主動層改善非晶氧化銦鎵鋅(a-IGZO)薄膜電晶體之電特性 30
3.1 實驗說明 30
3.2 元件製作前之量測 31
3.3 元件製作 34
3.4 結果與討論 40
3.4.1 元件特性之量測與討論 40
3.4.2 能量障壁之驗證 46
3.5 結論 50
Chapter 4 使用黃光微影技術改善非晶氧化銦鎵鋅(a-IGZO)薄膜電晶體之關閉漏電流 52
4.1 實驗說明 52
4.2 元件製作 53
4.2.1 閘極圖案化a-IGZO元件 53
4.2.2 以黃光微影圖案化閘極的雙主動層a-IGZO元件結構說明 57
4.3 結果與討論 59
4.4 結論 63
Chapter 5 結論與未來展望 64
參考文獻 66

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