臺灣博碩士論文加值系統

During the last decade, Solid State Drives (SSDs) which are composed of multiple NAND flash chips are replacing the hard disk drives (HDDs) in the mass storage market because the faster throughout, lower power consumption and other advantages. Unfortunately, the reliability become a critical issue when designing a large-scale flash storage. In order to balance the performance and reliability, Redundant Arrays of Inexpensive Disks (RAID) storage architecture become necessary to flash memory storage. However, how to handle the overhead of parity page which is aggressively updated data is also a considerable problem. Besides, NAND flash memory enable to operate a small portion of MLC/TLC flash memory blocks in SLC-mode to serve as write buffer. These SLC-mode blocks can absorb a large number of write operations. In this paper, we present a novel RAID technique for reducing the flash memory write stress. The key idea is to adopt well-known delta compression with partial programming and use the partial parity technique. We leverage the partial programming of SLC-mode flash memory pages to make sure that the original data and updated data of the original ones can reside in the same physical page. Then we also implement a small cache and separate it to two parts to delay the original parity and delta partial parity. Coincidentally, the partial programming technique and partial parity delay scheme are both design for decreasing the total page write count including parity page on flash memory based RAID system and we make those two techniques cooperate well by managing efficiently different page format such as data page, parity page and delta page and so on. In this way, we can reduce the write stress of overall RAID system and also accompany less erase count. Those analysis are evaluated by using a SSD customized simulator. The results show that our proposed scheme can largely reduce the write stress and erase count on flash memory pages with significant hot intensive traces.

During the last decade, Solid State Drives (SSDs) which are composed of multiple NAND flash chips are replacing the hard disk drives (HDDs) in the mass storage market because the faster throughout, lower power consumption and other advantages. Unfortunately, the reliability become a critical issue when designing a large-scale flash storage. In order to balance the performance and reliability, Redundant Arrays of Inexpensive Disks (RAID) storage architecture become necessary to flash memory storage. However, how to handle the overhead of parity page which is aggressively updated data is also a considerable problem. Besides, NAND flash memory enable to operate a small portion of MLC/TLC flash memory blocks in SLC-mode to serve as write buffer. These SLC-mode blocks can absorb a large number of write operations. In this paper, we present a novel RAID technique for reducing the flash memory write stress. The key idea is to adopt well-known delta compression with partial programming and use the partial parity technique. We leverage the partial programming of SLC-mode flash memory pages to make sure that the original data and updated data of the original ones can reside in the same physical page. Then we also implement a small cache and separate it to two parts to delay the original parity and delta partial parity. Coincidentally, the partial programming technique and partial parity delay scheme are both design for decreasing the total page write count including parity page on flash memory based RAID system and we make those two techniques cooperate well by managing efficiently different page format such as data page, parity page and delta page and so on. In this way, we can reduce the write stress of overall RAID system and also accompany less erase count. Those analysis are evaluated by using a SSD customized simulator. The results show that our proposed scheme can largely reduce the write stress and erase count on flash memory pages with significant hot intensive traces.

0.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
0.2 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . 7
0.2.1 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 7
0.2.2 RAID Technique . . . . . . . . . . . . . . . . . . . . . . . . . 8
0.2.3 Partial Parity Cache . . . . . . . . . . . . . . . . . . . . . . . . 9
0.2.4 Partial Programming . . . . . . . . . . . . . . . . . . . . . . . 10
0.2.5 Delta Compression . . . . . . . . . . . . . . . . . . . . . . . . 11
0.3 DCPD: Delta Compression and Parity Delay . . . . . . . . . . . . . . . 11
0.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
0.3.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . 12
0.3.3 Writing Operation . . . . . . . . . . . . . . . . . . . . . . . . 15
0.3.4 Cache Committing and Replacement . . . . . . . . . . . . . . . 22
0.3.5 Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
0.4 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
0.4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . 28
0.4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 30
0.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

[1] P. M. Chen, E. K. Lee, G. A. Gibson, R. H. Katz,
and D. A. Patterson, “Raid: High-performance, reliable sec-
ondary storage,” no. UCB/CSD-93-778, Nov 1993. [Online]. Available:
http://www2.eecs.berkeley.edu/Pubs/TechRpts/1993/6306.html
[2] X. Zhang, J. Li, H. Wang, K. Zhao, and T. Zhang, “Reducing solid-state stor-
age device write stress through opportunistic in-place delta compression,” 14th
USENIX Conference on File and Storage Technologies (FAST 16), pp. 111–124,
Feb. 2016.
[3] L. Yao, D. Liu, K. Zhong, L. Long, and Z. Shao, “Tlc-ftl: Workload-aware flash
translation layer for tlc/slc dual-mode flash memory in embedded systems,” pp.
831–834, Aug 2015.
[4] Y. Oh, E. Lee, J. Choi, D. Lee, and S. H. Noh, “Efficient use of low cost ssds for
cost effective solid state caches,” 2013.
[5] S. Im and D. Shin, “Flash-aware raid techniques for dependable and high-
performance flash memory ssd,” IEEE Transactions on Computers, vol. 60, no. 1,
pp. 80–92, Jan 2011.
[6] N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Pani-
grahy, “Design tradeoffs for ssd performance,” pp. 57–70, 2008.
[7] SAMSUNG, K9ABG08U0A Data Sheet, Std., 2009.
49[8] F. Chen, T. Luo, and X. Zhang, “Caftl: A content-aware flash translation layer
enhancing the lifespan of flash memory based solid state drives,” pp. 6–6, 2011.
[9] L. M. Grupp, J. D. Davis, and S. Swanson, “The bleak future of nand flash mem-
ory,” pp. 2–2, 2012.
[10] Y. Lu, J. Shu, and W. Zheng, “Extending the lifetime of flash-based storage
through reducing write amplification from file systems,” pp. 257–270, 2013.
[11] Y. Li, Y. Fong, and T. Miwa, “Non-volatile memory and control with improved
partial page program capability,” Oct. 27 2005, uS Patent App. 10/830,824.
[12] U. Manber and S. Wu, “Glimpse: A tool to search
through entire file systems,” pp. 4–4, 1994. [Online]. Available:
http://dl.acm.org/citation.cfm?id=1267074.1267078
[13] M. H. Philip Shilane, Grant Wallace and W. Hsu, “Delta compressed and dedupli-
cated storage using stream-informed locality,” 2012.
[14] C. B. Morrey and D. Grunwald, “Peabody: the time travelling disk,” pp. 241–253,
April 2003.
[15] Q. Yang and J. Ren, “I-cash: Intelligently coupled array of ssd and hdd,” pp.
278–289, Feb 2011.
[16] J. Li, K. Zhao, X. Zhang, J. Ma, M. Zhao, and T. Zhang, “How much can data
compressibility help to improve nand flash memory lifetime,” pp. 227–240, 2015.
[17] Q. Yang, W. Xiao, and J. Ren, “Trap-array: A disk array architecture providing
timely recovery to any point-in-time,” pp. 289–301, 2006.
[18] G. Wu and X. He, “Delta-ftl: Improving ssd lifetime via exploiting content local-
ity,” pp. 253–266, 2012.
50[19] L. P. Chang, “A hybrid approach to nand-flash-based solid-state disks,” IEEE
Transactions on Computers, vol. 59, no. 10, pp. 1337–1349, Oct 2010.
[20] L.-P. Chang and C.-D. Du, “Design and implementation of an efficient
wear-leveling algorithm for solid-state-disk microcontrollers,” ACM Trans. Des.
Autom. Electron. Syst., vol. 15, no. 1, pp. 6:1–6:36, Dec. 2009. [Online].
Available: http://doi.acm.org/10.1145/1640457.1640463
[21] UMassTraceRepository, “Oltp application i/o.” [Online]. Available:
http://traces.cs.umass.edu/index.php/Storage/Storage