臺灣博碩士論文加值系統

晶片網路架構(Network-on-Chip, NoC)以點對點封包架構取代了傳統的匯流排架構，此設計有效地解決了傳統大型系統晶片(System-on-Chip, SoC)內部溝通架構上的瓶頸，因此有越來越多的系統以晶片網路架構來建置。另一方面，隨著資訊安全變得重要，許多系統為了確保資料的安全性與隱密性，會利用加解密演算法將資料內容處理轉換，而進階加密標準(Advanced Encryption Standard, AES)演算法即為目前被廣泛使用的加解密演算法之一。許多系統都加入了加解密的硬體加速器，以加速資料處理的速度。然而，既有的AES硬體加速器皆沒有針對應用於以晶片網路為內部架構的系統所設計。若將目前的AES硬體加速器整合進晶片網路架構中，不僅無法發揮加速器效能，也對整體晶片網路的效率帶來極大的損害。為解決上述之問題，我們提出了一種適用於晶片網路架構中的AES硬體加速器，此加速器為一種多核心的架構設計，以平行運算的方式提升效能，而內部核心間的連結則以軟體定義晶片路架構(Software-Defined Network-on-Chip, SDNoC)來實現。我們所提出的軟體定義晶片網路架構將軟體定義網路 (Software-Defined Networking, SDN)的概念與晶片網路架構結合，相較於傳統的晶片網路，此設計可提升48%的傳輸效能與減少29%功率消耗。此外，因其架構具有可拓展性，此加速器可適用於各種以晶片網路為架構的環境中。

Network-on-Chip (NoC), which is a packet-based and multi-core architecture. It is considered to be a new generation of SoC and the solution for the interconnection problem of large-scale SoCs. Most AES related publications not designed for NoC could suffer the loss of efficiency in either area or performance and cause network congestion if directly porting them to a NoC-based environment. With inspections of resource sharing, packet format, interconnection and operation flow, we propose a Software Defined Network-on-Chip (SDNoC)-based AES accelerator. Our design base on the multicore architecture where the processing elements are interconnected using the SDNoC architecture to improve the efficiency of AES encryption/decryption process in the NoC-based environment. In this design, the processing element which executes AES process are architected. The SDNoC interconnection architecture which is the NoC architecture with the concept of Software-Defined Networking (SDN) can decrease the 48% packet delay and reduce 29% power consumption. With the scalable architecture, the proposed AES accelerator can support various performance demands by simply changing the number of PEs in designs.

RECOMMENDATION FORM I
COMMITTEE FORM II
CHINESE ABSTRACT III
ENGLISH ABSTRACT IV
ACKNOWLEDGEMENTS V
TABLE OF CONTENTS VII
LIST OF TABLES IX
LIST OF FIGURES X
CHAPTER 1 INTRODUCTION 1
1.1 Introduction of Network on Chip and Advanced Encryption Standard 1
1.2 Motivation 2
1.3 Organization 4
CHAPTER 2 ARCHITECTURE OF SDNOC-BASED AES ACCELERATOR 5
2.1 Hardware Architecture Overview 5
2.2 Analysis of AES Algorithm on The NoC-Based Environment 8
2.2.1 Encryption 10
2.2.2 Decryption 11
2.3 Design and Compress Routing Algorithm for SDNoC Router 12
CHAPTER 3 IMPLEMENTATION 19
3.1 AES-PE 19
3.1.1 Implementing Inv/SbuByte and Inv/ShiftRows Transformations 20
3.1.2 Implementing Inv/MixColumns, AddRoundKey, and Key Expansion 22
3.2 Packet-Based Configurations 23
3.2.1 Packet-Based Encryption 24
3.2.2 Packet-Based Decryption 26
3.3 SDN-Based Router 27
CHAPTER 4 EXPERIMENT 30
4.1 Interconnection Performance 30
4.2 Performance of AES Accelerator 34
CHAPTER 5 CONCLUSION 37
REFERENCE 38

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