臺灣博碩士論文加值系統

過去數十年裡，封包分類器一直被視為網路架構中最重要之一部分。而在現今網路世界中，由於越來越多應用如多媒體影音 (multimedia) 及物聯網 (IoT) 重視在傳輸品質及延遲等議題上，使得有效降低延遲之需求也急遽上升。另一方面，傳統五元組 (tuple) 標頭之網路封包已逐漸無法滿足現今網路之複雜度。被視為下一世代網路技術核心之軟體定義網路 (SDN) 隨之應運而生。軟體定義網路中所運用之協定 – OpenFlow 提供了十二元組或以上標頭格式做為解決方案，以因應當前應用之訴求。為改善上述問題，本篇論文中，我們針對延遲議題上，透過異質處理單元之設計與重組，提出『延遲壓縮』之封包分類器架構。經實驗結果指出，本篇所提出之方法可達頻率 303M 赫茲，並可支援三千條以上十二元組標頭格式之封包。相比於其他相關研究，本篇架構在封包處理之延遲部分，更可有效縮減達到2.18倍以上。

Packet classification has been recognized as one of the most significant functions in the network infrastructure over the past decade. Since more and more applications such as multimedia and IoTs have concerned about the propagation delay, the demand for low latency has increased dramatically. In addition, the traditional packet with fixed 5-tuple header fields does not suffice for today's requirement. OpenFlow having 12-tuple fields was proposed to support more complicated network interface such as Software Defined Networking (SDN) which has been proposed as a flexible paradigm for the next generation Internet provision. In this paper, we propose the Latency Compression Scheme (LCS) packet classification to ameliorate the latency issue by reorganizing heterogeneous processing element (PE). The proposed scheme was implemented on Xilinx Virtex-6 FPGA platform. The result shows that the proposed method can sustain 303 MHz, support all match types and contain 3K rules of 12-tuple fields. Essentially, the total period cost of entire packet improves at least 2.18× shorter than other solutions by applying the proposed architecture.

Chapter 1 Introduction
1.1 Introduction of Network Profile
1.2 Motivation
1.3 Challenges of Existing Works
1.4 Advantages of Platform on FPGA
1.5 Contributions
1.6 Organization
Chapter 2 Background
2.1 Traditional vs. OpenFlow Packet Classification
2.2 FPGA-based Engine for High-speed Networking
Chapter 3 Related Works
3.1 Packet Classification Techniques
3.2 Prior Works of Packet Classification
Chapter 4 Architecture
4.1 Exact/Prefix Search Unit
4.2 Range Search Unit
4.3 Modular Architecture
Chapter 5 Performance Evaluation
5.1 Experimental Setup and Resource Utilization
5.2 Performance Metrics and Comparisons
Chapter 6 Conclusion

[1] Software-Defined Networking (SDN) Definition. [Online]. Available: https://www.opennetworking.org/den-resources/den-definition.
[2] OpenFlow Switch Specification V1.0.0. [Online]. Available: http://archive.openflow.org/documents/openflow-spec-v1.0.0.pdf, 2009.
[3] M. Ojo et al., “An SDN-IoT Architecture with NFV Implementation,” in 2016 IEEE Globecom Workshops, 2016 © IEEE. doi: 10.1109/GLOCOMW.2016.7848825
[4] Y.-W. Ma et al., “SDN-enabled network virtualization for industry 4.0 based on IoTs and cloud computing,” in 19th Int. Conf. Advanced Communication Technology, Bongpyeong, South Korea, 2017, pp. 199-202.
[5] H. Ko et al., “SDN-based distributed mobility management for 5G,” in 2017 IEEE Int. Conf. Consumer Electronics, 2017 © IEEE. doi: 10.1109/ICCE.2017.7889250
[6] Y. Cui et al., “SDN-based Big Data Caching in ISP Networks,” IEEE Trans. Big Data, to be published.
[7] J. M. Llopis et al., “Minimizing Latency of Critical Traffic through SDN,” in 2016 IEEE Int. Conf. Networking, Architecture and Storage, 2016 © IEEE. doi: 10.1109/NAS.2016.7549408
[8] P. Schulz et al., “Latency Critical IoT Applications in 5G: Perspective on the Design of Radio Interface and Network Architecture,” IEEE Commun. Magazine, Vol. 55, no. 2, pp. 70-78, Feb., 2017.
[9] F. Yu et al., “Efficient Multimatch Packet Classification and Lookup with TCAM,” IEEE Micro, vol. 25, no. 1, pp. 50-59, 2005.
[10] K. Lakshminarayanan et al., “Algorithms for Advanced Packet Classification with Ternary CAMs,” in Proc. ACM SIGCOMM, 2005, pp. 193-204.
[11] S. Dharmapurikar et al., “Fast packet classification using bloom filters,” in Proc. ANCS, 2006, pp.61-70.
[12] H. Yu and R. Mahapatra, “A power- and throughput-efficient packet classifier with n bloom filters,” IEEE Trans. Comput., vol. 60, no. 8, pp. 1182-1193, Aug. 2011.
[13] W. Jiang and V. K. Prasanna, “Large-scale wire-speed packet classification on FPGAs,” in Proc. ACM/SIGDA Int. Symp. Field Programmable Gate Arrays, 2009, pp. 219-228.
[14] Y.-K. Chang and C.-S. Hsueh, “Range-Enhanced Packet Classification,” IEEE Trans. Emerging Topics in Computing, vol. 4, no. 2, pp. 214-224, Jun. 2016.
[15] Y. R. Qu and V. K. Prasanna, “High-Performance and Dynamically Updatable Packet Classification Engine on FPGA”, IEEE Trans. Parallel Distrib. Syst., vol. 27, no. 1, pp.197-209, Jan. 2016.
[16] Xilinx, Inc., San Jose, CA, “Xilinx Virtex-6 FPGA family,” 2009. [Online]. Available: http://www.xilinx.com/products/virtex6/
[17] H. Song and J. W. Lockwood, “Efficient packet classification for network intrusion detection using FPGA,” in Proc. ACM/SIGDA 13th Int. Symp. Field-programmable gate arrays, New York, NY, 2005, pp. 238-245
[18] T. Ganegedara et al., “A scalable and modular architecture for high-performance packet classification,” IEEE Trans. Parallel Distrib. Syst., vol. 25, no. 5, pp. 1135-1144, May. 2013.
[19] P. Gupta and N. McKeown, “Algorithms for packet classification,” IEEE Netw., vol. 15, no. 2, pp. 24-32, Mar. 2001.
[20] W. Jiang and V. K. Prasanna, “Scalable packet classification on FPGA,” IEEE Trans. VLSI Syst., vol. 20, no. 9, pp. 1668-1680, Sep. 2012.
[21] P. Gupta and N. McKeown, “Classifying packets with hierarchical intelligent cuttings,” IEEE Micro, vol. 20, no. 1, pp. 34-41, Feb. 2000.
[22] W. Jiang and V. K. Prasanna, “Field-split Parallel Architecture for High-Performance Multi-match Packet Classification using FPGAs,” in Proc. 21st Annu. Symp. Parallelism in Algorithms and Architectures, 2009, pp. 188-196.
[23] T. V. Lakshman and D. Stiliadis, “High-Speed Policy-Based Packet Forwarding Using Efficient Multi-Dimensional Range Matching," in Proc. ACM SIGCOMM, 1998, pp. 203-214.
[24] V. Srinivasan et al., “Fast and Scalable Layer Four Switching,” in Proc. ACM SIGCOMM, 1998, pp. 191-202.
[25] E. Spitznagel et al., “Packet Classification using extended TCAMs,” in Proc. IEEE Int. Conf. Network Protocols, 2003, pp. 120-131.
[26] T. Ganegedara and V. K. Prasanna, “StrideBV: Single chip 400G+ packet classification,” in Proc. IEEE 13th Int. Conf. High-Performance Switching and Routing, 2012, pp. 1-6.