臺灣博碩士論文加值系統

鎖相迴路（PLL）在無線頻率收發器（RF）中是非常重要的，PLL的功能包括相位檢測器（PFD），電荷泵（CP），環路濾波器（LF），壓控振盪器（VCO）和除頻器（FD），為了追求低功耗、低相位雜訊，寬鎖頻範圍是除頻器中最重要的特性。 本文介紹了注入鎖定除頻器（ILFD）的研究。
首先，提出了一種超寬鎖頻範圍之CMOS除2注入鎖定除頻器（ILFD）， 台積電製造的TSMC 0.18-μm CMOS ÷2 ILFD使用一對交叉耦合開關晶體管，直接雙注入MOSFET和RLC雙諧振諧振器，諧振器中包括含電阻的LC諧振器技術，用於降低諧振器的品質因數（Q），並獲得寬鎖頻範圍。 ÷2 ILFD內核的消耗功率為10.22 mW。
其次，介紹了使用TSMC 0.18-μm CMOS工藝的寬工作範圍並聯諧振除3注入鎖定除頻器（ILFD）， ÷3 ILFD電路透過並聯諧振交叉耦合的n-core MOS LC-tank振盪器實現，可調MOSFET電阻用於調節振盪頻率，並擴大工作範圍，串聯兩個直接注入MOSFET作為倍頻器和動態線性混頻器來擴大鎖定範圍。 ÷3 ILFD內核的消耗功率為6.12 mW。
第三，研究了TSMC 0.18-μm CMOS工藝中4th/6th RLC諧振之除2/4注入鎖定除頻器（ILFD）的鎖定範圍屬性。 分析其注入功率在-20 dBm到10 dBm之間的特性比較。
最後，研究了採用TSMC 0.18-μm 1P6M CMOS技術製造的一個LC除2注入鎖定除頻器（ILFD）之特性。 輸出緩衝區和焊盤的總面積為1.196×1.1939 mm2 ， 消耗功率為6.341 mW。

Phase-locked loop (PLL) is very notably important in radio-frequency (RF) transceivers. A PLL block includes the phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage controlledvoltage-controlled oscillator (VCO) and frequency divider (FD). Low power consumption, low phase noise, and a wide lock range, are the most important features of the FD. This thesis introduces the studiesy of the injection locking frequency divider (ILFD).
First, an ultra-wide-locking-range CMOS divide-by-2 injection-locked frequency dividers (ILFD) is presented. The fabricated 0.18-μm CMOS ÷2 ILFD uses a pair of cross-coupled switching transistors, direct-injection dual-injection MOSFETs and a RLC dual-resonance resonator. A technique with the degraded LC resonator, which by includes aing resistor in the resonator, is used to decrease the quality factor (Q) factor of the resonator and to obtain the wide-locking range. The consumed power of the ÷2 ILFD core is 10.22 mW.
Secondly, a wide- operation- range parallel resonant divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18-μm CMOS process is presented. The ÷3 ILFD circuit is realized with a parallel resonant cross-coupled n-core MOS LC-tank oscillator. A tunable MOSFET resistor is used to tune the oscillation frequency and widen the operation range. Two direct-injection MOSFETs in series are used as a double frequency and a dynamic linear mixer to widen the locking range. . The power consumption of the ILFD core is 6.12 mW.
Thirdly, we study the locking range property of the 4th/6th- order RLC-resonator divide-by-2/4 injection-locked frequency dividers (ILFDs) in the 0.18-μm CMOS process. The injection power is between -20 dBm to and 10 dBm, between which is one of the characteristics of in the comparison.
Finally, an LC tank divide-by-2 ILFD has been designed and fabricated in using the TSMC 0.18-μm 1P6M CMOS technology. The total die area, which includesing the output buffer and the pads, is 1.196×1.1939 mm2. The power consumption is 6.341 mW.

中文摘要 I
Abstract III
致謝 V
Table of ContentsTable of Contents VI
List of FiguresList of Figures VIII
List of TablesList of Tables XII
Chapter 1 Introduction 1
1.1 Background 1
Chapter 2 Design of Injection Locked Frequency Divider 4
2.1 Principle of Injection Locked Frequency Divider 5
2.2 Locking Range 7
Chapter 3 Degradation of the Resonator Q-factor to Enhance the Locking Range of the Divide-by-2 Injection-Locked Frequency Divider 10
3.1 Introduction 10
3.2 Circuit Design 13
3.3 Measurement Results 15
Chapter 4 Wide-Band ÷3 LC-Tank Injection-Locked Frequency Divider 21
4.1 Introduction 21
4.2 Circuit Design 23
4.3 Measurement Results 27
Chapter 5 Locking Range Property of Triple/Dual-Resonance Divide-by-2/4 Injection-Locked Frequency Divider at High Injection Power 33
5.1 Introduction 33
5.2 Dual-Resonance (DR) Divide-by-2/4 ILFD 34
5.3 Measurement Results 35
5.4 Triple-Resonance (TR) Divide-by-2 ILFD 41
5.5 Measurement Results 42
Chapter 6 Injection-Locked Frequency Divider Implemented with 6th-OrderLC Resonators 47
6.1 Introduction 47
6.2 Circuit Design 49
6.3 Measurement Results 50
Chapter 7 Conclusions 56
References 58

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