臺灣博碩士論文加值系統

超高精度的轉換器向來都極具市場重要性，但卻是相當難以設計的標的，需要極為審慎地處理製程變異所產生的系統性不匹配（Systematic Mismatch）與隨機性不匹配（Random Mismatch），方能成事。隨機性不匹配可以透過加大關鍵元件面積來抑制，但是系統性不匹配則須透過電路校準或精巧佈局才有可能解決。在數位至類比轉換器方面，西元1999 年有論文提出Q2 隨機漫步（Quad-Quad Random Walk）的佈局樣式，為14 位元轉換器成功立下小於0.3 LSB 積分非線性誤差（INL）的成就，迄今已近二十年，尚無人可以打破該精度的歷史紀錄！
本論文採用分段電流導向式(Segmented Current Steering)的架構，對線性度影響至鉅的高位元部分透過單位電流源矩陣來實現，主要是改造Random Walk 的概念來產生兩個子母矩陣，讓編號相連的元件儘量不相鄰，再透過子母矩陣相互嵌套成為初始佈局矩陣來大幅打亂相鄰電流源間的依存性，讓差分非線性誤差(DNL)趨近亂數化，以避免積分非線性誤差的累積。而後透過改良式Quad-Quad 的旋轉與鏡射(Mirroring)將此初始佈局矩陣複製16 份、均勻分佈在最終佈局大矩陣內，讓每個單位電流源皆由16個子電流源並聯而成，且該 16 個子電流源總共散佈在8個不同的x 座標與8個不同的y 座標上，使均勻度更甚以往，以打破14 位元數位至類比轉換器之歷史精度鴻溝與紀錄。
研究透過MATLAB 模擬製程變異下的INL，不論是拿Enhanced Q2 取代Q2、或是拿Random Pattern 來取代Random Walk，都可以獲致較好的INL，要是兩種技巧都以我們所發明者取代，可以發現Enhanced Q2 Random Pattern 的線性誤差比Q2Random Walk 平均小上6.07 倍，其有效位元數平均可以提高多達2.5 位元，紮實地證明所發明之Enhanced Q2 與Random Pattern 雙雙確實優於以往之Q2 與Random Walk。相關概念已與本校電機系方劭云教授的研究團隊合作，透過操控EDA 軟體來自動合成此電流源矩陣並以 MATLAB 行為模擬驗證其優秀精度。不過這僅僅是該些創新發明的觀念驗證，故本論文希望藉由獨創之嶄新佈局與電路設計一舉突破14 位元數位至類比轉換器之歷史精度水準，相關概念投稿至IEEE TCAD 並已被接受，即將刊登。

High accuracy data converters are always the hot spots of the application markets. However, they are really hard to design and engineers need to take a good care of the systematic and random mismatches of critical deices to achieve good enough accuracy. The random mismatch can be reduced by increasing the areas of critical devices. On the other hand, systematic mismatch can only be cancelled through circuit calibration or subtle layout patterns. For digital-to-analog converter (DAC), Q2 (Quad-Quad) Random Walk layout pattern was created in 1999 to achieve 0.3 LSB integral nonlinearity (INL) with 14-bit resolution. For more than 20 years till now, no designer on earth is capable of breaking this historical record in DAC accuracy.
A segmented matrix style current-steering DAC is proposed in this thesis. To enhance the linearity of Random Walk, Random Pattern is created to further randomize the positions among sequential current sources and thus minimize the correlations among their DNLs to prevent INL error accumulation. The mirroring and rotation of Quad-Quad are also modified to distribute the 16 sub-cells of each unary current sources into 8 x coordinates and 8 y coordinates instead of only 4 x coordinates and 8 y coordinates to get better uniformity.
Through MATLAB behavior simulations, the INL is reduced by replacing either Q2 with Enhanced Q2 or Random Walk with Random Pattern. On average, the INL of Enhanced Q2 Random Pattern is reduced from Q2 Random Walk by 6.07 times to increase almost 2.5 bits in the effective number of bits (ENOB). It thus proves the effectiveness and excellence of the proposed layout pattern. For implementation, some script and constraints are composed by Prof. Shao-Yun Fang and her Ph.D. student to guide the EDA tool for Automatic Placement and Routing (APR) according to the new matrix style layout pattern. The post simulations show that the proposed Enhanced Q2 Random Pattern is much better than the traditional Q2 Random Walk in accuracy. The idea was submitted to the top CAD journal, IEEE Transactions on Computer-Aided Design, and the paper was accepted already for future publication.

摘要 I
Abstract II
誌謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章 緒論 1
1-1 研究背景與動機 1
1-2 相關研究發展與概要 2
1-3 研究目標與方法 3
1-4 論文架構 4
第二章 數位至類比轉換器的基本原理 5
2-1 理想數位至類比轉換器 5
2-2 理想數位至類比轉換器特性 6
2-3 數位至類比轉換器之規格參數 7
2-3-1 靜態參數 7
2-3-2 動態參數 12
2-4 數位至類比轉換器之架構簡介 16
2-4-1 解碼器轉換器架構 16
2-4-2 二進位權重式轉換器架構 18
2-4-3 溫度計碼式轉換器架構 22
2-4-4 混合式轉換器架構 24
2-5 結論 25
第三章 數位至類比轉換器之設計考量 26
3-1 電流源電晶體不匹配特性 26
3-2 電流源的有限輸出阻抗分析 31
3-3 電流源開關電晶體的非理想效應 35
3-4 電流源頻寬分析 36
3-5 控制訊號耦合效應 37
3-6結論 38
第四章 數位至類比轉換器電路設計與佈局實現 39
4-1 改良式Q2隨機佈局樣式 40
4-2 分段式數位至類比轉換器架構 47
4-3 佈局規劃 52
4-4 高位元電流源矩陣設計 54
4-4-1 單位電流源尺寸選擇 54
4-4-2 單位電流源架構 55
4-4-3 利用Verilog-A行為模擬電流源特性 56
4-4-4 高位元單位電流源矩陣之走線規則 58
4-4-5 高位元單位電流源矩陣之佈局考量 59
4-4 低位元電流源陣列設計 62
4-5 去突波升壓電路設計 64
4-6 電流緩衝器與輔助電流源設計 65
4-7 解碼器設計 67
4-8 偏壓電路設計 68
4-9 脈鐘驅動電路 69
第五章 晶片模擬結果及未來展望 70
5-1 晶片佈局圖 70
5-1 靜態模擬結果 71
5-2 動態模擬結果 74
5-4 晶片效能比較 84
5-5 量測板規劃 84
5-6 量測方法 85
5-7 結論與未來展望 86
參考文獻 87

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