臺灣博碩士論文加值系統

本論文旨在探討圖騰柱功因修正器電路傳導性電磁干擾抑制技術，參考文獻推導電路模型，並模擬與實測圖騰柱功因修正器電路之傳導性電磁干擾雜訊。本文的推導過程可分為兩大部分：首先為被動元件分析，探討高頻時的等效電路模型；然後考量功率開關和傳導路徑，針對圖騰柱功因修正器進行電路分析。將兩者的等效電路結合以電腦軟體模擬，再與實際量測結果相互比較，且利用降低PFC電感寄生電容抑制電路雜訊。
本論文透過模擬與實測被動元件之阻抗與相位曲線，再套用電路模型以進行傳導性電磁干擾之電路模擬分析。最後將模擬的雜訊與實際量測的結果做比較，以探討電路模型的可行性。

關鍵字：圖騰柱功因修正器、傳導性電磁干擾、被動元件、功率開關

This thesis aims to study the suppression techniques of conducted electromagnetic interference (EMI) for totem-pole power Factor correction (PFC) circuit. By literature survey, circuit models are derived and verified by simulation and measurement of conducted EMI of totem-pole PFC. The model derivation in this thesis can be divided into two parts: firstly, high-frequency equivalents of the passive components are studied and discussed. Then, equivalent models of power switches and noise conducted path of totem-pole PFC circuit are analyzed. Finally, these two parts are combined and simulated by computer software. The results are compared and verified by actual measurement. In addition, the parasitic capacitance of PFC choke is reduced to suppress the circuit noise.
In this thesis, the impedance and phase curves of passive components are simulated and measured. Then, the conducted EMI is simulated and analyzed by the circuit model. The simulation results are compared with actual measured noise to verify the feasibility of developed circuit model.

摘要 i
Abstract ii
誌 謝 iii
目錄 iv
圖表目錄 vi
第一章 緒論 1
1.1 研究背景和動機 1
1.2 研究目的和方法 2
1.3 論文大綱 3
第二章 電磁干擾量測簡介 4
2.1 電磁相容簡介 4
2.2 電磁干擾法規規範 5
2.3 傳導性電磁干擾量測原理 8
2.4 電源傳輸阻抗穩定網路之工作原理 13
2.5 共模及差模雜訊介紹 15
2.6 雜訊分離器工作原理 16
第三章 電路元件之高頻特性分析 19
3.1電路架構 19
3.2電感高頻模型建立與推導 20
3.3電容高頻模型建立與推導 24
3.4主電感高頻模型建立與推導 25
3.4電源傳輸阻抗穩定網路 27
第四章 電路模型推導、模擬與實測 29
4.1圖騰柱功率因數修正器電路推導模型 29
4.2圖騰柱功率因數修正器電路模擬 31
4.3圖騰柱功率因數修正器電路實測 32
4.4圖騰柱功率因數修正器電路雜訊改善 35
第五章 結論與未來展望 43
5.1結論 43
5.2未來展望 44
參考文獻 45

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