臺灣博碩士論文加值系統

本論文著重在於CMOS製程下，設計出一個高性能且滿足高解析度要求的類比數位轉換器(Analog-to-Digital Converter, ADC)，可以用於通訊與影像中。我們設計出一個十四位元每秒一億次取樣之管線逐次逼近式類比數位轉換器，利用數位校正技術來提高ADC的解析度，滿足系統所要求的規格。早期使用的架構，以管線式類比數位轉換器(Pipelined ADC)為主要的設計方向。速度是管線式類比數位轉換器的優點。但是，它的缺點是會消耗很大的功率。 近年來ADC研究的方向趨向低功耗的設計，越來越多人研究具有省電優勢的逐次逼近式類比數位轉換器(Successive Approximation Register ADC, SAR ADC)。逐次逼近式類比數位轉換器由比較器、放大器、取樣電路、電容陣列和數位電路所構成，用二進位逼近法，漸進的找到輸入訊號，來達成轉換的工作原理。因此，在速度的比較上，管線式類比數位轉換器會比逐次逼近式類比數位轉換器快。
在此篇論文中，我們使用管線式逐次逼近式類比數位轉換器，採用逐次逼近式類比數位轉換器為主要的架構來達到省電的目的。另外，加入管線式的排程概念，一級取樣一級轉換，更有效率的使用時間，讓速度更加提升。由於兩級間的剩餘放大器 (Residue amplifier)，會有非線性的增益誤差。因此，我們利用數位校正處理器，針對線性與非線性誤差做校正，讓剩餘放大器經由數位校正電路可以趨近一個理想的放大器。

The thesis focuses on designing a high-performance Analog-to-Digital converter (ADC) in CMOS fabrication. In addition, the ADC needs to achieve a high-resolution requirement in order to apply communication and graphic system. Accordingly, we design a 14-bit 100MS/s pipelined-SAR ADC. Furthermore, using background calibration to improve linearity and be compatible with the system’s requirement. In early works, pipelined ADC was the major architecture that had been researched and designed for many years. The reason is that pipelined ADC has an advantage of speed. However, its drawback is that it consumes a lot of power to achieve high-speed. In recent years, researches and papers dedicated to invent low power architecture. More and more people studied successive approximation register ADC (SAR ADC) for its advantage of energy efficiency. The architecture of SAR ADC contains comparator, amplifier, sample and hold circuit, capacitor array, and digital logics. SAR ADC uses binary searching method to convert analog signals into digital codes. Thus, comparing the speed to pipelined ADC, SAR ADC has a little bit slower than pipelined ADC.
In this thesis, we introduce a pipelined-SAR ADC. It is based on SAR ADC architecture in order to achieve energy efficiency. Considering to the speed, pipelined-SAR consists the conversion method of pipelined ADC. It uses two stages to do the evaluation. While one stage is sampling, the other is converting. Therefore, with pipelined ADC operation style, pipelined-SAR ADC is able to wisely use a full cycle of time and accelerate the speed. The nonlinearity gain error of residue amplifier may influence pipelined-SAR ADC's resolution. We apply a digital calibration system to correct linearity and nonlinearity errors. After nonlinearity is removed, the residue amplifier is approximately to be a linear amplifier.

論文摘要 I
Abstract II
誌謝 IV
Contents V
List of Figures VIII
List of Tables XII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Survey of Prior Works 5
1.3 Motivation 8
Chapter 2 Calibration Algorithm 11
2.1 Introduction 11
2.2 Basic Concepts 13
2.3 Lyapunov-Based Calibration 15
2.4 MATLAB Simulation 24
Chapter 3 ADC architecture 28
3.1 Introduction 28
3.2 Proposed ADC Architecture 34
3.2.1 First stage 35
3.2.2 Second stage 39
3.3 Issues & Techniques 42
Chapter 4 Circuit Implementation 44
4.1 ADC1 47
4.1.1 Sample and Hold circuit 49
Linearity requirement 50
Issues 51
Bootstrapping Switch 54
Layout 58
4.1.2 Comparators 59
Noise 61
Performance 61
Offset issue 61
Layout 62
4.1.3 Digital to Analog Convertor 63
KT/C requirement 63
Mismatch requirement 65
Common-mode Voltage issue 67
Splitting capacitor method 68
Binary Window technique 73
Capacitor Swapping technique 75
4.1.4 SAR Control logic 81
4.2 Residue Amplifier 83
4.2.1 Linearity Requirement 83
4.2.2 Architecture 85
Performance 86
4.2.3 Nonlinearity Background Calibration 88
4.3 ADC2 93
4.3.1 Sample and Hold circuit 95
4.3.2 Comparator 97
4.3.3 Digital to Analog Convertor 100
KT/C requirement 100
Mismatch requirement 100
Switch Back method 101
Capacitor Swapping technique 104
4.3.4 SAR control 106
4.4 Calibration Processor 108
4.4.1 Random injection 108
4.4.2 Injection amount 109
4.5 Layout information 112
Chapter 5 Simulation Results 113
5.1 Pre-Layout Simulation 113
5.2 Post-Layout Simulation 117
Chapter 6 Conclusions and Future works 121
6.1 Conclusions 121
6.2 Future works 122
Bibliography 124

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