臺灣博碩士論文加值系統

近年來，錯誤修正碼 (ECC) 技術與內建自我修復 (BISR) 技術皆被廣泛地使用來提升記憶體的良率與可靠度。錯誤修正碼技術以及內建自我修復技術主要分別用來處理軟錯誤與硬錯誤。而在過去有許多研究探討使用錯誤修正碼修復硬錯誤來進一步提升良率。然而，使用錯誤修正碼修復硬錯誤會對記憶體的可靠度造成衝擊，受錯誤修正碼保護的編碼字位址便不能再容忍額外的軟錯誤發生。另一方面，硬錯誤的數量是會隨著時間慢慢累積的。所以當記憶體的使用時間拉長到一定年限時，發生的錯誤數量極有可能會超出錯誤修正碼的負荷。為了改善這些問題，本論文提出使用部分時間冗餘技術之多位元硬錯誤遮蔽 (Multiple Permanent Fault Masking, MPFM) 技術，可以在不影響錯誤修正碼的修正能力下即時修正在編碼字中超過一個以上的硬錯誤。
在修復分析時，利用錯誤修正碼修復單錯誤的故障編碼字，並將發生多個位元錯誤的故障編碼字位址儲存起來。在正常使用模式下，要對這些故障編碼字位址執行寫入指令時，執行額外的讀取動作並比較寫入與讀取的資料，接著可以得知哪些位置被激發出錯誤。再將編碼字變補、寫回記憶體，最後再次讀取編碼字，可藉由比較兩次讀取的資料得知硬錯誤位置，有了硬錯誤位置和激發出錯誤的位置後，便能夠判斷每個硬錯誤的激發狀況，再運用少許的位元將激發狀況記錄下來；當要對這些位址執行讀取指令時，可以再次以相同的額外讀寫動作得到硬錯誤位置，接著只要運用先前在寫入指令時記錄的硬錯誤激發情況將有被激發出硬錯誤的位置變補後，即可將一個編碼字中多個硬錯誤一併修正。
本研究不僅僅實現了MPFM技術的硬體架構，更對修復率、可靠度、效能損失與額外硬體成本做了詳盡的分析。實驗結果顯示MPFM技術能夠顯著地改善良率及可靠度，並且效能損失以及額外的硬體成本皆小至可忽略的程度。

To improve the fabrication yield and reliability of embedded memories, error correction code (ECC) and built-in self-repair (BISR) techniques are widely used to deal with soft errors and hard errors in recent years, respectively. There are also some previous techniques proposed to handle hard errors by ECC for further enhancing the fabrication yield. However, these techniques incur significant impact on the reliability of the target memories since some of the ECC protection capabilities are used for repairing hard errors. Furthermore, they still cannot correct multiple hard errors. In this thesis, a multiple permanent fault masking (MPFM) scheme based on the partial time redundancy concept is proposed. With the MPFM technique, we can correct multiple hard errors and soft errors contained in a codeword simultaneously.
In the power-on test and repair stage, MPFM uses ECC to repair single hard errors first and store the codeword addresses containing multiple hard errors. When the memory system is used on-line and executes a write operation, the faulty codeword will be complemented and written back again. We then read out the complemented codeword from the memory after the first write operation. With the above operations, we can know the activation status of each hard error. The activation situations are then stored. During the read operation, similar extra operations are executed for obtaining the hard error locations. Thereafter, the stored activation situations can be used to correct those hard errors.
The corresponding hardware architecture of the MPFM technique is also proposed in this thesis. A simulator is implemented to evaluate repair rate, reliability, hardware overhead (HO), and performance penalty (PP). Experimental results show that the proposed technique can improve yield and reliability significantly with nearly negligible HO and PP.

致謝 I
摘要 II
Abstract III
目錄 V
圖目錄 IX
表目錄 XI
第一章 簡介 1
1.1 動機及背景 1
1.2 組織架構 4
第二章 靜態隨機存取記憶體內建自我測試、診斷和修復技術 5
2.1 基本元件及特性 5
2.2 故障模型 7
2.3 測試演算法 9
2.4 內建自我測試 11
2.5 內建自我診斷與修復 12
第三章 錯誤檢查及修正技術 16
3.1 錯誤修正碼 16
3.1.1 錯誤偵測與修正 16
3.1.2 漢明碼 17
3.1.3 修正漢明碼 (Modified Hamming Code) 18
3.1.4 蕭氏碼 19
3.2 時間冗餘之硬錯誤即時修正技術 20
3.2.1 單位元硬錯誤遮蔽技術 20
3.2.2 雙位元硬錯誤即時修正技術 22
第四章 使用部分時間冗餘技術提升嵌入式記憶體之可靠度與良率 24
4.1 基於部分時間冗餘之多位元硬錯誤遮蔽技術簡介 24
4.2 記憶體測試與硬錯誤修復流程 25
4.2.1 內建自我修復流程 26
4.2.2 內建自我修復流程範例 27
4.3 正常使用模式操作流程 30
4.3.1 寫入操作流程 31
4.3.2 讀取操作流程 33
4.3.3 硬錯誤即時修正範例 34
4.4 多位元硬錯誤遮蔽技術硬體架構 38
4.4.1 多位元硬錯誤遮蔽技術整體硬體架構 38
4.4.2 錯誤修正碼編碼器與解碼器 41
4.4.3 硬錯誤遮蔽內容定址記憶體模組 (Multiple Permanent Fault CAM Module) 43
4.4.4 硬錯誤修正模組 (Hard Error Corrector Module) 44
第五章 實驗結果 49
5.1 修復率分析 49
5.1.1 瑕疵分布與故障型態設定 49
5.1.2 模擬器環境設定 51
5.1.3 修復率模擬結果 53
5.2 可靠度分析 56
5.2.1 可靠度模型 56
5.2.2 可靠度模擬結果 59
5.3 效能損失分析 61
5.3.1 效能損失模型 61
5.3.2 效能損失分析結果 63
5.4 硬體成本分析 63
5.4.1 硬體成本估算模型 64
5.4.2 硬體成本分析結果 69
5.5 超大型積體電路實現 72
第六章 結論與未來展望 74
6.1 結論 74
6.2 未來展望 74
參考文獻 75

[1] Semico Res. Corp., Phoenix, AZ, USA, ASIC IP Rep., 2007. [Online]. Available: https://semico.com/content/semico-systems-chip-%E2%80%93-braver-new-world
[2] Richard Bowles, “Memory resiliency,” Intel® Technology Journal, vol. 17, issue. 1, pp. 1-200, 2013.
[3] R. C. Baumann, “Soft errors in advanced semiconductor devices—Part I: The three radiation sources,” IEEE Trans. Device and Materials Reliability, vol. 1, no. 1, pp. 17-22, Mar. 2001.
[4] D. C. Bossen, and M. Y. Hsiao, “A system solution to the memory soft error problem,” IBM Journal of Research and Development, vol. 24, no. 3, pp. 390-397, May 1980.
[5] W. Kuo, W. T. K. Chien, and T. Kim, “Reliability, yield, and stress burn-in,” Kluwer Academic Publishers, Boston, 1998
[6] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), pp. 995-1001, Oct. 2001.
[7] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int’l Test Conf. (ITC), pp. 567-574, Oct. 2000.
[8] C. T. Huang, C. F. Wu, J. F. Li, and C. W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. Rel., vol. 52, no. 4, pp. 386–399, Dec. 2003.
[9] S. K. Lu, C. L. Yang, Y. C. Hsiao, and C. W. Wu, “Efficient BISR techniques for embedded memories considering cluster faults,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 184–193, Feb. 2010.
[10] M. Lee, L. M. Denq, and C. W. Wu, “A memory built-in self-repair scheme based on configurable spares,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 6, pp. 919–929, Jun. 2011
[11] Y. T. J. Chen, J. F. Li, and T. W. Tseng, “Cost-efficient built-in redundancy analysis with optimal repair rate for RAMs,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, no. 6, pp. 930–940, June 2012.
[12] W. Kang, H. Cho, J. Lee, and S. Kang, “A BIRA for memories with an optimal repair rate using spare memories for area reduction,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp. 2336–2349, Nov. 2014.
[13] A. J. van de Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8-14, Mar. 1993.
[14] S. Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays,” IEEE Design and Test of Computers, vol. 4, no. 1, pp. 24-31, June 1987.
[15] T. H. Wu, P. Y. Chen, M. Lee, B. Y. Lin, C. W. Wu, C. H. Tien, H. C. Lin, H. Chen, C. N. Peng, and M. J. Wang, “A memory yield improvement scheme combining built-in self-repair and error correction codes,” in Proc. Int. Test Conf., pp. 1-9, Nov. 2012.
[16] S. K. Lu, H. H. Huang, J. L. Huang, and P. Ning, “Synergistic reliability and yield enhancement techniques for embedded SRAMs,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 165–169, Jan. 2013.
[17] C. Argyrides, P. Reviriego, and J. A. Maestro, “Using single error correction codes to protect against isolated defects and soft errors,” IEEE Trans. Rel., vol. 62, no. 1, pp. 238–243, Mar. 2013.
[18] S. K. Lu, C. J. Tsai, and M. Hashizume, “Enhanced built-in self-repair techniques for improving fabrication yield and reliability of embedded memories” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 6, pp. 921–932, June 2016.
[19] Ashok K. Sharma, “Static random access memory technologies,” Advanced Semiconductor Memories:Architectures, Designs, and Applications, Wiley-IEEE Press eBook Chapters, pp. 19-127, 2003.
[20] J. M. Rabaey, A.Chandrakasan, and B. Nikolic “Digital integrated circuits,” Pearson Education Taiwan Ltd.
[21] Michael L. Bushnell, Vishwani D. Agrawal, “Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits,” Kluwer Academic Publishers, 2000.
[22] J. van de Goor, Zai Al-Ars, “Functional memory faults: a formal notation and a taxonomy,” in Proc. IEEE VLSI Test Symposium, pp. 281-289, Apr. 2000.
[23] R. Nair, S. M. Thatte, and J. A. Abraham, “Efficient algorithms for testing SRAMs,” IEEE Trans. on Computers, vol. C-27, no. 6, pp. 572-576, June 1978.
[24] R. Dekker, F. Bennker, and L. Thijssen, “Fault modeling and test algorithm development for static random access memories,” in Proc. Int’l Test Conf., pp. 343-352, Sep. 1988.
[25] A. J. Van De Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8-14, Mar. 1993.
[26] M. L. Bushnell and V. D. Agrawal, “Essentials of electronic testing,” Kluwer Academic Publishers, 2000.
[27] http://www.syntest.com/
[28] http://www.hoy-tech.com/
[29] M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories,” Electronics, pp. 175-179, Jan. 1984.
[30] R. W. Hamming, “Error detecting and error correcting codes,” Bell System Tech. J., vol. XXVI, no. 2, pp. 147-160, Apr. 1950.
[31] K. Pagiamtzis and A. Sheikholeslami, “Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 712–727, Mar. 2006.
[32] C. H. Stapper, F. M. Armstrong, and K. Saji, “Integrated circuit yield statistics,” Proceedings of the IEEE, vol. 71, no. 4, pp. 453-470, Apr. 1983.
[33] R. F. Huang, J. F. Li, J. C. Yeh, and C. W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories,” in Proc. IEEE Int. Workshop Mem. Technol., Des. Testing (MTDT), pp. 68–73, July 2002.