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研究生:蔡政宏
研究生(外文):CAI, ZHENG-HONG
論文名稱:改良BAST中PRPG的LFSR電路以減少BAST所需的測試數據量
論文名稱(外文):A Modified BAST for Test Data Reduction Using Correlation of ATPG Pattern
指導教授:蔡亮宙
口試委員:程毓明黃慶祥蔡亮宙
口試日期:2017-06-28
學位類別:碩士
校院名稱:南臺科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:52
中文關鍵詞:BAST檢測
外文關鍵詞:PRPGBISTBAST
相關次數:
  • 被引用被引用:0
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  • 下載下載:17
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在工廠中,製造汽車、火箭、冰箱、坦克、飛機等較危險的產品時,我們往往希望出場時它不會是個故障品,畢竟關係的人的生命,所以工廠往往有很多的故障檢測方法,以確保送到消費者手上的產品是沒有故障疑慮的,但檢測故障時往往得花上大量的時間和金錢,這對企業所期待的利益與產品安全是很難兩全的,因此這製作產品時加入檢測電路故障晶片,是相當普遍的也節省成本與時間,相關技術也不斷被提出,但為了使成本與時間所使用的晶片需要性能要求降低,我們必須減少晶片所需的Test Data。

本研究為了成本考量,改良檢測電路故障晶片技術之一被稱作BAST (BIST Aided Scan Test)的技術,能夠在使用BAST時減少所需的Test Data是在好不過的。所以我們改良了PRPG (Pseudo Random Pattern Generators),基於ATPG (Automatic Test Pattern Generation) 模式所產生的關聯表,在LFSR裡插入MUX(Multiplexer)跟NOT gate來減少BAST所需的Test Data。

具體程序是我們基於PRPG模式和ATPG模式中的Scan chain所製作的關聯表來產生控制訊號給LFSR電路進行feedback。且基於ATPG模式所製作關聯表在LFSR裡插入額外MUX跟NOT gate,也提出了改良LFSR電路的feedback方法。基於ATPG模式所製作關聯表我們加入了MUX,而MUX的位置的決定方法,我們使用了ATPG模式所製作關聯表,在ATPG模式和PRPG模式中有same、different、don't care值,我們依照這三個值定義了三個基準值,在依照這三個基準值去決定MUX使用何種關聯表來決定位置。

最後我們使用了ISCAS89 和 ITC99電路來做為我們的Target電路,我們的實驗結果使用了13個Target電路來做比較,比起以往的實驗,我們的研究結果能節省15-56%的test data。

In order to reduce the test data for BAST (BIST-Aided Scan Test), an LFSR reseeding circuit with additional MUXs (Multiplexer) and NOT gates are proposed.

The procedure to generate the control signals for optimal reseeding of the circuit are proposed by making correlation tables based on matching between PRPG (Pseudo Random Pattern Generators) pattern and ATPG (Automatic Test Pattern Generation) pattern slice.

I enhanced the structure of the LFSR by adding extra MUXes and NOT gates based on correlation table of ATPG pattern. A reseeding method for the enhanced LFSR is also proposed. MUXes are added based on correlation table of ATPG patterns. To select position of extra MUXes, a suitable correlation table is chosen by the normalized value of the correlation tables (same, different, don't care).

Experimentation and evaluation of test data volume for ISCAS89 and ITC99 benchmark circuit are conducted. I applied the proposed procedure for 13 benchmark circuits. The procedure can achieve about 15-56% reduction in test data for BAST.

第一章 介紹
第二章 用於DFT(Design-for-testability)的同步順序電路
2.1 Scan-based BIST (Built-In Self Test)
2.2 BAST (BIST-Aided Scan Test)
第三章 BAST中Reseeding控制訊號決定法
3.1 生成循環控制PRPG的操控信號
3.2 Pruning方法1:Pruning不必要的搜索
3.3 Pruning方法2:使用 state matrix
3.4 Pruning方法3:在最後結果中進行局部改良
第四章 基於分析ATPG模式的關聯表控制LFSR reseeding
4.1 改良LFSR電路
4.2 ATPG slice的關聯表
4.3 關聯表的normalized value
4.4 選擇關聯表並添加MUX於LFSR的方法
4.4.0 選於LFSR中插入MUX和NOT GATE的方法
4.4.1 選擇關聯表(Same plus Don't care)
4.4.2 選擇關聯表(Same minus Conflict)
4.4.3 4.4.3 選擇關聯表(Same)
4.5 提出方法的實驗結果
4.6 提出方法的評價
第五章 基於ATPG模式中Don't care value的比例選擇關聯表
5.1 基於Don't care value的比例來選擇MUX的關聯表
5.2 提出方法的評價
第六章 結論
參考文獻


1.T. Hiraide, K. O. Boateng, H. Konishi, K. Itaya, M. Emori, H. Yamanaka and T. Mochiyama, “BIST-Aided Scan Test - A New Method for Test Cost Reduction," Proc. VLSI Test Symposium, pp. 359-364, 2003.
2.C-C. Fang, H. Yotsuyanagi, and M. Hashizume, “A Test Pattern Matching Method on BAST Architecture for Test Data Reduction by Controlling Scan Shift,” IEEE Workshop on RTL and High Level Testing, 2014.
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6.N. A. Touba, E. J. McCluskey, “Synthesis of mapping logic for generating transformed pseudo-random patterns for BIST,” Proc. ITC, pp. 674 - 682,1995.
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on BAST Architecture to Reduce Bit-flipping and Skipping of Random Patterns,” 2014 Shikoku-section joint convention record of the institutes of electrical and related engineers, p.114, 2014.
9.M. Yamamoto, H. Yotsuyanagi and M. Hashizume, “Scan chain configuration for BIST-aided scan test using compatible scan flip-flops,” Workshop on RTL and High Level Testing, pp. 99-104, 2008.
10.T. Hosokawa, Y. Chen, L. Wan, M. Wakazono, M. Yoshimura, “A Test Pattern Matching Method on BAST Architecture Using Don't Care Identification for Random Pattern Resistant Faults,” Proc. ITC, pp. 738-743, 2010.
11.W.-C. Lien, K.-J. Lee, T.-Y.Hsieh, “A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume,” IEEE 21st Asian Test Symposium, pp.278-283, 2012.
12.R. Mori, H. Yotsuyanagi and M. Hashizume, “Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code,” IEICE Tech. Rep., vol.113, no. 430, pp. 5560, 2014 (in Japanese).
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