臺灣博碩士論文加值系統

本篇論文主要使用矽基底鰭式電晶體(Bulk Si FinFET)製程製作射頻鰭式場效電晶體，由於製程技術進步，元件尺寸縮小，短通道效應將影響元件特性，我們採用三維結構，鰭式場效電晶體能有效的抑制短通效應。為了運用在射頻應用上，元件佈局上採用了多指(Multi-finger)閘極的結構，並同時使用多重鰭(Multi-fin)的結構，以此來減少閘極電阻並增加汲極電流和元件的總寬度，來提升轉導值。但因為鰭式場效電晶體為三維結構，它有較大的寄生電容，因此它的速度被限制住。為了減少它的寄生電容，在元件佈局方面修改射頻鰭式場效電晶體的各尺寸參數，設計出一套不同尺寸參數的元件，最後我們提出梳型源/汲極接觸區結構的RF FinFET，並比較不同尺寸參數與結構的元件，找出元件佈局的準則。
而為了使元件能使用在射頻功率的應用上，我們將DEMOS的技術運用在FinFET，並提出兩種新的結構，來改善傳統汲極延展FinFET的崩潰電壓與導通電阻的權衡關係，並比較不同尺寸參數與結構對元件的對元件直流與高頻特性的影響，找出元件佈局的準則，以適用在射頻功率應用。
在元件量測方面對鰭式場效電晶體元件進行直流特性分析和高頻S參數量測，直流特性分析包括轉導特性、導通電阻和崩潰電壓；而S參數量測主要是萃取元件的截止頻率和最大震盪頻率。對不同尺寸參數與結構的元件進行量測，比較不同尺寸參數與結構對元件特性的影響，最後透過元件佈局設計上的改良，做出一個給予未來設計射頻與功率應用之鰭式場效電晶體的一個指標參考。

With reducing the gate length of MOSFETs in advanced process technology, the short channel effects would be problematic. In recent years, FinFETs were developed to enable control of the short channel effects. We study the FinFET technology for RF and power applications in this thesis. RF and power FinFETs were fabricated using a bulk-Si FinFET process. For RF applications, devices were designed with a multi-fin and multi-gate layout to reduce the gate resistance and increase the total drain current as well as transconductance. However, FinFETs exhibit higher parasitic capacitances due to their 3-D structures. Therefore, the speed of FinFETs is limited. To reduce the parasitic capacitances, we modified and designed the devices with different geometrical parameters. Besides, a novel device layout with a pectinate S/D contact area was proposed. Through the characterization of devices with different geometries, we found a guideline for device layout design.
For power applications, the DEMOS technology was adopted in our FinFET devices. Conventional drain-extended FinFETs have a trade-off between breakdown voltage and on- resistance. To solve this problem, we proposed two types of power FinFET structures. By analyzing the DC and high-frequency characteristics, including transconductance, breakdown voltage, cutoff frequency and maximum oscillation frequency, we found a design guideline for RF power FinFETs.

目錄

摘　要 i
ABSTRACT iii
誌 謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第一章 緒論 1
1.1 研究目的與介紹 1
1.2文獻回顧 5
1.3論文架構 9
第二章 元件製作與設計方法 10
2.1 研究方法 10
2.2 RF FinFET與RF Power FinFET元件製程 10
2.2.1主動層製作 11
2.2.2閘極製作、摻雜(N+/P+) 11
2.2.3後段製程 12
2.3 元件佈局設計 15
第三章 射頻鰭式電晶體之特性分析 18
3.1 簡介 18
3.2 不同源/汲極延展長度之比較 20
3.3不同鰭間距之比較 26
3.4不同指根數目與鰭數目之比較 30
3.5 梳型源/汲極接觸區結構之元件特性 35
3.6 結論 38
第四章 射頻功率鰭式電晶體之特性分析 40
4.1 簡介 40
4.2 RF Power FinFET的直流特性 42
4.3 RF Power FinFET的高頻特性 50
4.4 結論 53
第五章 結論 54
參考文獻 55

[1]D. Lederer, B. Parvais, A. Mercha, N. Collaert, M. Jurczak, J.-P. Raskin,and S. Decoutere, “Dependence of FinFET RF performance on fin width,” in Proc. 6th Top. Meeting SiRF, San Diego, CA, Jan. 18–20, 2006, pp. 4–6..
[2]B. Parvais, V. Subramanian, A. Mercha, M. Dehan, P. Wambacq, W. Sanssen, G. Groeseneken, S. Decoutere. “FinFET technology for analog and RF circuits”, IEEE Conference on Electronics, Circuits and Systems, pp. 182-185, 2007.
[3]B. Parvais, M. Dehan, V. Subramanian, A. Mercha, K. Tamer San, M. Jurczak, “ Analysis of the FinFET parasitics for improved RF performances ” IEEE International SOI Conf, pp 37-38, 2007.
[4]C.-C. Yeh, C.-S. Chang, H.-N. Lin, W.-H. Tseng, L.-S. Lai, T.-H. Perng, T.-L. Lee, C.-Y. Chang, L.-G. Yao, C.-C. Chen, T.-M. Kuan, J. J. Xu, C.-C. Ho, T.-C. Chen, S.-S. Lin, H.-J. Tao, M. Cao, C.-H. Chang, T.-C. Ko, N.-K. Chen, S.-C. Chen, C.-P. Lin, H.-C. Lin, C.-Y. Chan, H.-T. Lin, S.-T. Yang, J.-C. Sheu, C.-Y. Fu, S.-T. Hung, F. Yuan, M.-F. Shieh, C.-F. Hu, and C. Wann, “A Low Operating Power FinFET Transistor Module Featuring Scaled Gate Stack and Strain Engineering for 32/28nm SoC Technology,” IEDM Tech. Dig., pp. 34.1.1-34.1.4, 2010
[5]M. Fulde, D. Schmitt-Landsiedel and G. Knoblinger1. “Analog and RF design issues in high-k & multi-gate CMOS technologies,” IEDM Tech. Dig., pp. 1-1, 2009,
[6]C.-H. Jan, M. Agostinelli, M. Buehler, Z.-P. Chen, S.-J. Choi, G. Curello, H. Deshpande, S. Gannavaram, W. Hafez, U. Jalan, M. Kang, P. Kolar, K. Komeyli, B. Landau, A. Lake, N. Lazo, S.-H. Lee, T. Leo, J. Lin, N. Lindert, S. Ma, L. McGill, C. Meining, A. Paliwal, J. Park, K. Phoa, I. Post, N. Pradhan, M. Prince, A. Rahman, J. Rizk, L. Rockford, G. Sacks, A. Schmitx, H. Tashiro, C. Tsai, P. Vandervoorn, J. Xu, L. Yang, J.-Y. Yeh, J. Yip, K. Zhang, Y. Zhang, and P. Bai, “A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications,” IEDM Tech. Dig., pp. 1-4, 2009.
[7]J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices,” IEDM Tech. Dig., pp. 437, 2001.
[8]V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert, M. Jurczak, G. Groesenken, W. Sansen, and S. Decoutere, Solid-State Electron, Impact of fin width on digital and analog performances of n-FinFETs,” vol 51, no. 4, pp. 551-559. Apr. 2007.
[9]D. J. Frank, Y. Taur, and H. -S. P. Wong “Future prospects for Si CMOS technology,” in Device Research Conference, 1999, pp. 18-21.
[10]J. C. Tinoco, S. S. Rodriguez, A. G. Martinez-Lopez, J. Alvarado and J. P. Raskin, “Impact of extrinsic capacitances on FinFET RF performance”, IEEE Transactions on Microwave Theory and Techniques, vol. 61, no.2, pp. 833- 840, 2013.
[11]M. Guillorn, J. Chang, A. Bryant, N. Fuller, O. Dokumaci, X. Wang, J. Newbury, K. Babich, J. Ott, B. Haran, R. Yu, C. Lavoie, D. Klaus, Y. Zhang, E. Sikorski, W. Graham, B. To, M. Lofaro, J. Tornello, D. Koli, B. Yang, A. Pyzyna, D. Neumeyer, M. Khater, A. Yagishita, H. Kawasaki and W. Haensch, “FinFET performance advantage at 22 nm: an AC perspective”, IEEE Symp. VLSI Technology, pp. 12-13, 2008.
[12]P. Wambacq, B. Verbruggen, K.n Scheir, J. Borremans, V. D. Heyn, G. V. der Plas, A. Mercha, B. Parvais, V. Subramanian, M. Jurczak, S. Decoutere, S. Donnay, “Analog and RF circuits in 45-nm CMOS and below: planar bulk versus FinFET,” Proc. Eur. Solid-State Ciruits Conf., Montreux, Switzerland, pp. 53–56, 2006.
[13]P. Wambacq, B. Verbruggen, K. Scheir, J. Borremans, M. Dehan, D. Linten, V. D. Heyn, G. V. der Plas, A. Mercha, B. Parvais, C. Gustin, V. Subramanian, N. Collaert, M. Jurczak, and S. Decoutere, “The potential of FinFET for analog and RF circuit applications", IEEE Trans. Circuits Syst. I Reg. Papers, vol. 54, no. 11, pp. 2541-2551, Nov. 2007.
[14]G. Revathy, A. Rajak, “A survey on FinFETs: technology, pros, cons and improvement prospects”, IJAES, vol 2, no 10, Oct. 2014.
[15]V. Subramanian, B. Parvais, J. Borremans, A. Mercha, D. Linten, P. Wambacq, J. Loo, M. Dehan, C. Gustin, N. Collaert, S. Kubicek, R. Lander, J. Hooker, F. Cubaynes, S. Donnay,M. Jurczak, G. Groeseneken, W. Sansen, and S. Decoutere, ”Planar bulk MOSFETs versus FinFETs: an analog/RF perspective”. IEEE Trans. Electron Devices 12, pp.3071–3079, 2006.
[16]T. C. Lim, A. Kranti and G. A. Armstrong, “Performance assessment of nanoscale multiple gate MOSFETs (MuGFETs) for RF applications,” in Eur. Microw. Integr. Circuit Conf., EuMIC, Oct. 2006. pp. 141–142.
[17]M. Shrivastava, H. Gossner, V. R. Rao, “A Novel Drain-Extended FinFET Device for High-Voltage High-Speed Applications,” IEEE Electron Device Letters, vol. 33, no. 10, pp. 1432, 2012.
[18]T. Miyashita, K.C. Kwong, P.H. Wu, B.C. Hsu, P.N. Chen, C.H. Tsai, M.C. Chiang, C.Y. Lin, and S.Y. Wu., “High Voltage I/O FinFET Device Optimization for 16nm System-on-a-Chip (SoC) Technology”, Proc. Symp. VLSI Tech, pp. T152 - T153, 2015.
[19]B. Y. Chen, K. M. Chen, C. S. Chiu, G. W. Huang, H. C. Chen, C. C. Chen, F. K. Hsueh, M. C. Chen and E. Y. Chang, “RF power FinFET transistors with a wide drain-extended fin,” Jpn. J. Appl. Phys. vol. 56, no. 4S, pp. 04CR09, 2017.
[20]J. C. Mitros, C. Y. Tsai, H. Shichijo, K. Kunz, A. Morton, D. Good paster, D. Mosher, and T. R. Efland, “High-voltage drain extended MOS transistors for 0.18-um logic CMOS process,” IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1751-1755. 2001.
[21]M. Vermandel, C. De Backere and A. Van Calster, "A high voltage nDMOS structure in a standard sub-micron CMOS process", Proc. ESSDERC , pp. 508-511, 1997.
[22]H. Ballan and M. Declercq, “High Voltage Devices and Circuits in Standard CMOS Technologies “, Springer, New York, 1998, Chap. 3.
[23]B. J. Baliga, “Trends in power semiconductor devices,” IEEE Trans. Electron Devices vol.43, pp.1717-1731, 1996.
[24]P. Moens, B. Vlachakis, F. Bauwens, and L. DeSchepper, “Spatial distribution of interface traps in DeMOS transistors,” IEEE Trans. Electron Devices, vol, 25, pp. 577-579, 2004.
[25]P. Moens, F. Bauwens, M. Nelson, and M. Tack, “Electron trapping and interface trap generation in drain extended PMOS transistors,” Proc. IRPS, 2005, pp. 17-21.
[26]C. Duvvury, D. Briggs, J. Rodrigues, F. Carvajal, A. Young, D. Redwine and M. Smayling, “Efficient npn operation in high voltage NMOSFET for ESD robustness,” IEDM Tech. Dig., pp. 10-13, 1995.
[27]R. A. Bianchi, C. Raynaud, F. Blanchet, F. Monsieur, and O. Noblanc,” High voltage devices in advanced CMOS technologies,” IEEE Custom Integrated Circuits Conf., 2009, pp. 13-16.
[28]D. Muller, A. Giry, F. Judong, C. Rossato, F. Blanchet, B. Szelag, A. M. Aguirre, R. Sommet, D. Pache, and O. Noblance, “High-Performance 15-V Novel LDMOS Transistor Architecture in a 0.25- μm BiCMOS Process for RF-Power Applications,” IEEE Trans. Electron Devices, vol. 54, pp. 861-868, 2007.
[29]B. Szelag, H. Baudry, D. Muller, A. Giry, D. Lenoble, B. Reynard, D. Pache and A. Monroy, “Integration and Optimisation of a high performance of RF Lateral DMOS in an advanced BiCMOS Technology,” in Proc. IEEE Conf., 2003 , pp.39-42.
[30]Z. Lee, R. Zwingman, J. Zheng, W. Cai, P. Hurwitz, and M. Racanelli, “ A Modular 0.18 um Analog / RFCMOS Technology Comprising 32 GHz FT RF-LDMOS and 40V Complementary MOSFET Devices”, Bipolar/BiCMOS Circuits and Technology Meet. (BCTM), 2006, pp.8-10.
[31]K. E. Ehwald, A. Fischer, F. Fuernhammer, W. Winkler, B. Senapati, R. Barth, D. Bolze, B. Heinemann, D. Knoll, H. Ruecker, D. Schmidt, I. Shevchnko, R. Sorge, and H.-E. Wulf, “A two mask complementary LDMOS module integrated in a 0.25um SiGe:C BiCMOS platform” , European Solid-State Device Research, 2004, pp. 23.
[32]N. R. Mohapatra, H. Ruecker, K. E. Ehwald, R. Sorge, R. Barth, P. Schley, D. Schmidt, and H. E. Wulf, “A complementary RF-LDMOS architecture compatible with 0.13 μm CMOS technology,” Proc. Int. Symp. Power Semiconductor Devices and ICs, June. 2006, pp. 1-4
[33]G. Baldwin, J. Ai, K. Benaissa, F. Chen, P. R. Chidambaram, S. Ekbote, S. Ghneim, S. Liu, C. Machala, F. Mehrad, D. Mosher, G. Pollack, T. Tran, B. Williams, J. Yang, S. Yang, and F. S. Johnson, “90 nm CMOS RF technology with 9.0 V I/O capability for single-chip radio,” Symp. VLSI Technology Dig. Tech. Pap., June. 2003, pp. 10-12.
[34]T. Yan, H. Liao, Y. Z. Xiong, R. Zeng, J. Shi, and R. Huang, “Cost-Effective Integrated RF Power Transistor in 0.18-µm CMOS Technology,” IEEE Electron Device Letters., vol. 27, pp. 856-858, 2006.
[35]A. Mai and H. Rucker,, “Drain-extended MOS transistors capable for operation at 10 V and at radio frequencies,” Solid-State Device Research Conference (ESSDERC)., Sept. 2010, pp. 10-12.
[36]S. Nuttinck, B. Parvais, G. Curatola, and A. Mercha, “Double-Gate Finfets as a CMOS technology downscaling option: An RF perspective,” IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 279–283, Feb. 2007.
[37]R. Wang, J. Zhuge, R. Huang, Y. Tian, H. Xiao, L. Zhang, C. Li, X. Zhang, and Y. Wang, “Analog/RF performance of Si nanowire MOSFETs and the impact of process variation,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1288–1294, Jun. 2007.
[38]D. Yang, Y. Ding, and S. Huang, “A 65-nm high-frequency low noise CMOS-based RF SoC technology,” IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 328–335, Jan. 2010.
[39]Suhas N.Yadav, M.S.Jadhav, “Multiple Gate Field-Effect Transistors for Future CMOS Technologies” IETE Technical Review, vol. 7, no. 6, pp. 446-454, 2010.
[40]A. Kranti, G.Armstrong, “Comparative analysis of nanoscale MOS device architectures for RF applications” Semicond. Sci. Technol, vol. 22, no. 5, pp. 481-491, 2007
[41]T. C. Lim and G. A. Armstronga, “The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance,” Solid-State Electron., vol. 50, no. 5, pp. 774-783, 2006.
[42]J. Appels and H. Vaes, “High voltage thin layer devices (RESURF devices),” IEDM Tech. Dig., pp. 238-241, 1979.