臺灣博碩士論文加值系統

熱載子(hot carrier，HC)一直是主要的可靠度研究課題，早期的研究顯示，相較於nMOSFETs，pMOSFETs之熱載子劣化通常被忽略，這是由於電洞之平均自由路徑較小，載子遷移於約只有電子的三分之一，較難發生衝擊游離，再加上對於電洞而言，Si-SiO2之介面能障約為4.5eV，小於電子之3.2eV，所以在相同情況下，熱電洞注入氧化層之 機率比起熱電子來的小。然而隨著元件尺寸的微縮以及高介電材料之應用，pMOSFETs之熱載子劣化已嚴重到不可忽視的程度。故本篇論文以研究奈米等級之pMOSFETs於室溫下之熱載子效應與其恢復效應。
實驗元件是由聯華電子所提供的28nm製程的pMOSFETs，通道長度為0.035 µm，其閘極介電層為鉿鋯鉿之氧化層(HfOx/ZrOx/HfOx)，是利用原子沉積技術(ALD)製作而成。首先針對不同通道的元件作通道熱載子實驗(Vd=Vg=-1.7 V)，其結果發現短通道元件(L=0.035 µm)仍然存在熱載子劣化的問題，會使|ΔVt|上升以及降低導通電流。接著使用不同閘極電壓(相同汲極電壓)對短通道元件進行應力測試，結果發現在較大的閘極電壓下，不只會增加衝擊游離發生對汲極端之劣化，也會增加穿隧效應對源極端的劣化，此外，較大的閘極電壓同樣會影響通道中之載子濃度而增強載子之散射效應，使元件之劣化更加嚴重。利用源汲端交換量測以及計算ΔNit & ΔNot來分析熱載子劣化之位置，結果顯示劣化似乎是均勻地分布在整個通道，且劣化大部分發生在介電層中為主。接下來量測臨界電壓與閘極電流之關係，計算出在熱載子劣化中，冷載子的劣化約佔全部劣化之6~12%。
本篇研究最後一個主題是劣化後之恢復效應，一共使用了四種不同的偏壓方法，結果顯示，方法MD(Vg=0.8V，Vb= -0.8V，其他接地)之恢復效果最佳，大約能恢復臨界電壓之43.2%，推測其原因是由於閘極端正電壓以及基極端負電壓皆有助於將造成劣化之電洞排出，且經計算ΔNit & ΔNot後，發現其主要恢復發生於介電層中。在未來可以嘗試不同之偏壓方法以及加入溫度來探討熱載子之劣化以及恢復之特性。

Hot carrier (HC) effect has always been the major reliability issue to study. In early re-searches, the hot carrier induced degradation in pMOSFETs is negligible which was com-pared with nMOSFETs. It’s owing to the mean free path of holes is less than electrons and the mobility of hole is about one third than electron, in general, hole is more difficult to occur im-pact ionization then electron. Furthermore, the barrier of Si-SiO2 interface is about 4.5eV, which is higher than electron, which is about 3.2eV, so at the same situation, the probability of hot hole to get into the dielectric is less than the hot electron. However, with the shrinking of the device and the application of high-k dielectric, the hot carrier induced degradation in pMOSFETs can’t be ignored.
In this work, we use 28nm wafer with channel length 0.035μm and 0.2μm, which is provided by UMC. The hafnium-based gate dielectric with a profile of HfxZryOz ( HfOx/ZrOx/HfOx ) is made with atomic layer deposition (ALD) technology. At the be-ginning of this research, hot carrier stress was performed with long and short channel, and the result indicated that the short channel device (L=0.035μm) still had a problem with hot carrier degradation, which will increase |ΔVt | and decrease the on-current. After that, stress the short channel device with different gate voltage (at same drain voltage). The results show that, higher gate voltage will cause more degradation, because higher gate voltage will increase the number of the inversion charge, more inversion charge may not only enhance the impact ionization but increase the carrier-carrier scattering. Furthermore, by using reverse source drain measurement and calculate the interface states and oxide trapped charges to analyze the position of the hot carrier degradation. The experimental data show that the damage region is less localized and more uniformly distributed in the channel and the degradation is mainly happened in dielectric. Moreover, by observing the dependence between gate current density (Jg) and Vt shift to decoupling the cold carrier component from hot carrier degradation, which is about 6~12%.
The final topic of this study is the recovery phenomena, using four kinds of biased method to recover the degraded devices. The method MD had the best recovery rate, which is about 43.2%, we assumed the mechanism is that the trapped hole will be repel by positive bias on gate terminal and negative bias on bulk terminal, and the recovery is mainly happened in high-k dielectric. In the future, using different recovery method or considering the temperature effect on hot carrier degradation and recovery phenomena can be studied.

摘　要 i
ABSTRACT iii
誌謝 v
CONTENTS vi
LIST OF TABLES ix
LIST OF FIGURES x
Chapter 1 INTRODUCTION 1
1.1 Background 1
1.2 Thesis Organization 2
Chapter 2 BASIC PROPERTY OF MOSFETS 3
2.1 Research about Hgh-k/Metal gate dielectric 3
2.1.1 From Silicon Dioxide to High-k Dielectrics 3
2.1.2 The high density of defects in Hf-based dielectrics 7
2.1.3 Characteristic of HfO2 Dielectrics MOSFETs 8
2.2 Research about tunneling phenomena 10
2.2.1 Fowler-Nordheim tunneling 10
2.2.2 Direct tunneling 12
2.2.3 Band to Band tunneling 13
2.2.4 Poole-Frenkel tunneling 14
2.3 Research about Hot Carrier Effect 15
2.3.1 Hot Carrier Effect 15
2.3.2 Mechanism 16
2.4 Research about recovery phenomena 19
2.4.1 Recovery phenomena 19
2.4.2 Mechanism 20
Chapter 3 EXPERIMENTAL DESIGNS 21
3.1 Experimental Procedures 21
3.2 Experimental Structure Process 22
3.3 Measurement and Stress Conditions 23
3.3.1 Hot carrier stress measurement 23
3.3.2 Decouple the cold carrier component from hot carrier degradation 25
3.3.3 Reverse source/drain measurement 27
3.3.4 Hot carrier and recovery measurement conditions 29
Chapter 4 RESULTS AND DISCUSSION 31
4.1 Initial electrical characteristics of pMOSFETs 31
4.2 HC issues 34
4.2.1 HC stress induced degradation 34
4.2.2 Decouple the cold carrier component from hot carrier degradation 35
4.2.3 The degradation position of the hot carrier stress. 41
4.3 Recovery issues 43
4.3.1 Natural recovery after HC stress 43
4.3.2 The recovery method with applying bias 44
4.3.2 Mechanism 49
Chapter 5 CONCLUSION AND FUTURE WORKS 52
5.1 Conclusions 52
5.2 Future Works 53
REFERENCES 54
作者簡介 VITA 54

[1]R. Hegde, D. Triyoso, S. Samavedam, and B. White Jr, "Hafnium zirconate gate dielectric for advanced gate stack applications," Journal of applied physics, vol. 101, no. 7, p. 074113, 2007.
[2]H. Kim, Y. Roh, J. Lee, H.-B. Kang, C.-W. Yang, and N.-E. Lee, "Characteristics of high-k gate dielectric formed by the oxidation of sputtered Hf/Zr/Hf thin films on the Si substrate," Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 22, no. 4, pp. 1342-1346, 2004.
[3]C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, "Hot-electron-induced MOSFET degradation-model, monitor, and improvement," IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 295-305, 1985.
[4]H. Wong, "The current conduction issues in high-k gate dielectrics," in Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on, 2007, pp. 31-36: IEEE.
[5]G. D. Wilk, R. M. Wallace, and J. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations," Journal of applied physics, vol. 89, no. 10, pp. 5243-5275, 2001.
[6]J. Robertson, "Electronic structure and band offsets of high-dielectric-constant gate oxides," Mrs Bulletin, vol. 27, no. 03, pp. 217-221, 2002.
[7]T. Hori, Gate dielectrics and MOS ULSIs: principles, technologies and applications. Springer Science & Business Media, 2012.
[8]E. Gusev et al., "Ultrathin high-K metal oxides on silicon: processing, characterization and integration issues," Microelectronic Engineering, vol. 59, no. 1, pp. 341-349, 2001.
[9]J. Robertson, "High dielectric constant oxides," The European physical journal applied physics, vol. 28, no. 3, pp. 265-291, 2004.
[10]S. Pae et al., "BTI reliability of 45 nm high-K+ metal-gate process technology," in Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, 2008, pp. 352-357: IEEE.
[11]H. Park, M. Hasan, M. Jo, and H. Hwang, "Metal gate and high-k gate dielectrics for sub 50 nm high performance MOSFETs," Electronic Materials Letters, vol. 3, no. 2, pp. 75-85, 2007.
[12]R. Hegde et al., "Microstructure modified HfO2/using Zr addition with Tax/C/sub y/gate for improved device performance and reliability," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 35-38: IEEE.
[13]M. Koyama et al., "Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics," in Electron Devices Meeting, 2002. IEDM02. International, 2002, pp. 849-852: IEEE.
[14]Q. Lu et al., "Hot carrier reliability of n-MOSFET with ultra-thin HfO2/gate dielectric and poly-Si gate," in Reliability Physics Symposium Proceedings, 2002. 40th Annual, 2002, pp. 429-430: IEEE.
[15]E. Gusev et al., "Ultrathin high-K gate stacks for advanced CMOS devices," in Electron Devices Meeting, 2001. IEDM01. Technical Digest. International, 2001, pp. 20.1. 1-20.1. 4: IEEE.
[16]J. Robertson, "Band offsets of wide-band-gap oxides and implications for future electronic devices," Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, vol. 18, no. 3, pp. 1785-1791, 2000.
[17]G. Wilk and R. Wallace, "Electrical properties of hafnium silicate gate dielectrics deposited directly on silicon," Applied Physics Letters, vol. 74, no. 19, pp. 2854-2856, 1999.
[18]L. Pantisano et al., "Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide," in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, pp. 163-164: IEEE.
[19]G. Ribes et al., "Review on high-k dielectrics reliability issues," IEEE Transactions on Device and materials Reliability, vol. 5, no. 1, pp. 5-19, 2005.
[20]Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices. Cambridge university press, 2013.
[21]M. Lenzlinger and E. Snow, "Fowler‐Nordheim tunneling into thermally grown SiO2," Journal of Applied physics, vol. 40, no. 1, pp. 278-283, 1969.
[22]F.-C. Chiu, "A review on conduction mechanisms in dielectric films," Advances in Materials Science and Engineering, vol. 2014, 2014.
[23]E. O. Kane, "Theory of tunneling," Journal of Applied Physics, vol. 32, no. 1, pp. 83-91, 1961.
[24]W. L. F. A. G. Chynoweth, C. A. Lee, R. A. Logan, G. L. Pearson, and P. Aigrain,, "International field emission at narrow silicon and germanium p-n junctions," phys. Rev., vol. 118, pp. 425-434, 1960.
[25]Y. Taur et al., "CMOS scaling into the 21st century: 0.1 µm and beyond," IBM Journal of Research and Development, vol. 39, no. 1.2, pp. 245-260, 1995.
[26]R. t. group, Semiconductor reliability handbook. 2008.
[27]J.-Y. Tsai et al., "Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks," Applied Physics Letters, vol. 105, no. 14, p. 143505, 2014.
[28]R. Radojcic, "Hot-electron aging in p-channel MOSFETs for VLSI CMOS," IEEE Transactions on Electron Devices, vol. 31, no. 12, pp. 1896-1898, 1984.
[29]T. Tsuchiya and J. Frey, "Relationship between hot-electrons/holes and degradation of p-and n-channel MOSFETs," IEEE Electron Device Letters, vol. 6, no. 1, pp. 8-11, 1985.
[30]K. Ng, G. Taylor, and A. Sinha, "Instability of MOSFETs due to redistribution of oxide charges," IEEE Transactions on Electron Devices, vol. 29, no. 8, pp. 1323-1330, 1982.
[31]S. T. Chang, N. Johnson, and S. Lyon, "Capture and tunnel emission of electrons by deep levels in ultrathin nitrided oxides on silicon," Applied Physics Letters, vol. 44, no. 3, pp. 316-318, 1984.
[32]T.-C. Ong, M. Levi, P.-K. Ko, and C. Hu, "Recovery of threshold voltage after hot-carrier stressing," IEEE transactions on electron devices, vol. 35, no. 7, pp. 978-984, 1988.
[33]N. Hwang, B. Or, and L. Forbes, "Tunneling and thermal emission of electrons from a distribution of deep traps in SiO2," IEEE Transactions on Electron Devices, vol. 40, no. 6, pp. 1100-1103, 1993.
[34]B. H. Lee et al., "Validity of constant voltage stress based reliability assessment of high-/spl kappa/devices," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 1, pp. 20-25, 2005.
[35]M. Quevedo-Lopez et al., "High performance gate first HfSiON dielectric satisfying 45nm node requirements," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 4 pp.-428: IEEE.
[36]A. Masada, I. Hirano, S. Fukatsu, and Y. Mitani, "Method of Decoupling the Bias Temperature Instability Component from Hot Carrier Degradation in Ultrathin High-k Metal–Oxide–Semiconductor Field-Effect Transistors," Japanese Journal of Applied Physics, vol. 49, no. 7R, p. 071102, 2010.
[37]M. P. Pagey, "Characterization and modeling of hot-carrier degradation in sub-micron NMOSFETS," Citeseer, 2002.
[38]Y. Mitani, S. Fukatsu, D. Hagishima, and K. Matsuzawa, "Separation of NBTI component from channel hot carrier degradation in pMOSFETs focusing on recovery phenomenon," in IC Design & Technology (ICICDT), 2011 IEEE International Conference on, 2011, pp. 1-4: IEEE.
[39]J. Franco et al., "On the recoverable and permanent components of hot carrier and NBTI in Si pMOSFETs and their implications in Si 0.45 Ge 0.55 pMOSFETs," in Reliability Physics Symposium (IRPS), 2011 IEEE International, 2011, pp. 6A. 4.1-6A. 4.6: Ieee.
[40]P. McWhorter and P. Winokur, "Simple technique for separating the effects of interface traps and trapped‐oxide charge in metal‐oxide‐semiconductor transistors," Applied physics letters, vol. 48, no. 2, pp. 133-135, 1986.