臺灣博碩士論文加值系統

近年來行動裝置盛行，元件的待機狀態的漏電將是一個很重要的課題。本研究主要探討元件在未導通情況下的漏電流情形，研究分成兩個部分做討論，第一部分探討元件nMOS在負的閘極偏壓下其電流流動分布，第二部分探討元件在關狀態(off-state)下的各種漏電流機制，並比較不同通道與不同氮化退火製程下對這些漏電機制的影響。
本研究使用聯華電子所提供的28 nm nMOSFETs。前半部分測試在閘極負電壓的情況下、源極與基底接地、汲極加工作電壓與閘極在負電壓下掃描，觀察元件四個端點的電流分布。發現前半段電流由IG與IB主導，且非常大。在負的閘極電壓掃描下，基底電流會有電流流向的改變。後半部分討論元件在off-state狀態下的漏電機制，主要有汲極PN接面的漏電、DIBL漏電、汲極空乏區貫穿的漏電、閘極漏電流與GIDL漏電，此部分將使用不同通道長度、寬度與不同製程，加以探討。
實驗結果顯示負的閘極偏壓下IG與IB很大此為實驗元件為了要穩定臨界電壓VT值在佈局時上串聯了一個保護二極體，電流為此二極體在順向偏壓下所造成的。基底電流方向的變化為垂直電場造成的穿隧現象與GIDL漏電機制的變化。正端的漏電方面，PN接面漏電受到通道長度與製程方面的影響很小、但寬度會影響汲極端PN接面的面積造成接面漏電的變化。DIBL效應造成次臨界特性曲線平移，貫穿現象則造成次臨界特性斜率改變。在汲極電壓持續增加下，不管是長或短通道，貫穿現象都會比PN接面崩潰早發生。閘極漏電流方面，在DPN 600~800°C 退火並用大於10%的N2濃度退火得到的漏電最大，而在經過加壓測試之後，閘極漏電流在三種製程晶片中都由上升的情形，發現DPN 600~800°C退火與小於10%N2濃度褪火的閘極漏電流增加幅度最大。GIDL漏電方面，三種製程差異在較大的負閘極偏壓下較為明顯。
本研究對nMOSFETs在關狀態下有一定的研究價值，未來研究可探討不同溫度、氧化層厚度、汲極淺摻雜深度與氧化製程下的介面品質的影響。

In the recent year, mobile devices are very prevalent. The off-state current of these device is very important to keep the long-time operation. In this study, we focus on the off-state leakage. This thesis is separated into two parts. First part will discuss the current of nMOSFETs device in negative gate bias. Second part will probe some leakage mechanisms in off-state condition and then compare them in different channel lengths, DPN nitrogen concentrations and annealing temperatures.
In this study, we adopt the 28nm HK/MG wafers fabricated by UMC to do the related extraction and analysis. In first part, the basic experimental condition was that we applied a positive drain voltage (VDD). Source and bulk were grounded, gate voltage was swept in negative region. We observed all leakage for four terminals, and analyze that gate and bulk currents were very high, dominating most of leakage. We also find that the direction of bulk current flow will reverse when VG is -0.22 V. It cause by tunneling and GIDL effect.
Second part we discuss the leakage mechanisms in off-state, including PN junction in drain side reverse-bias current, DIBL current, GIDL current and punch through current. The experiment results show that the high IG and IB in negative gate bias are caused by a protection diode series with the device which is used to stable the threshold voltage. This high gate voltage induces that the diode has been turn on in the positive bias. The bulk current reverse is caused by tunneling current and GIDL mechanism. In the positive side, PN junction reverse-bias current is unrelated to the channel length and process, but changed by channel width. DIBL effect is more influences in short channel device, and cause subthreshold characteristic shift. When punch-through occurred, the S.S will changed. No matter what short or long channel device is, the punch-through is occured before PN junction breakdown in high drain voltage. In terms of gate leakage will obviously degrade in voltage stress. GIDL current has different between each process in high negative gate bias. DPN treatment with 600~800°C under 10% N2 has the most serious degradation in voltage stress.
This research has the value of reference to explain the effect of off-state leakage for nMOSFETs. In the future, this study can be extended to probe the relationship among temperature stress, equivalent oxide thicknesses, junction depth with LDD process, etc.

摘 要 i
ABSTRACT iii
致 謝 v
LIST OF TABLES ix
LIST OF FIGURES x
Chapter 1. 1
INTRODUCTION 1
1.1 Preview 1
1.2 Thesis Organization 2
Chapter 2. HIGH-K GATE DIELECTRICS 3
2.1 Trend of Device Shrinkage 3
2.2 The Replacement from SiO2 to High-k Dielectrics 4
2.2.1 Introduction of hafnium zirconate gate dielectric 7
2.2.2 ZrO2 position effect of ALD HfZrOx gate dielectric 9
2.2.3 The high density of defects in Hf-based dielectrics 11
2.3 Leakage Current of Off-state Device 13
2.3.1 PN junction reverse-bias current 14
2.3.2 Drain-induced barrier lowering (DIBL) and punch-through mechanism 15
2.3.3 Gate leakage 17
2.3.4 Gate-induced drain leakage 17
2.4 Research about Tunneling mechanism 19
2.4.1 Band-to-band tunneling 19
2.4.2 Direct tunneling 19
2.4.3 Fowler-Nordheim tunneling 20
2.4.4 Poole-Frenkel emission 21
2.4.5 Tunneling current in negative bias 22
Chapter 3. EXPERIMENTAL DESIGNS 25
3.1 Experimental Procedures 25
3.2 Experimental Structure Process 27
3.3 Measurement Conditions 28
Chapter 4. RESULTS AND DICUSSION 30
4.1 Electrical Characteristics with Different Channel Lengths 30
4.1.1 ID-VD characteristic 30
4.1.2 ID-VG charateristics 33
4.2 The research of the negative gate bias 35
4.2.1 Current of four terminals in negative bias 35
4.2.2 Tolerance of the gate oxide 37
4.2.3 Analysis of the two tunneling paths. 39
4.2.4 Research of the turning point of bulk current 40
4.3 Research of the off-state leakage 42
4.3.1 Reverse bias current for PN junction 43
4.3.2 Drain induced barrier lowering and punch-though effect 44
4.3.3 Gate leakage 50
4.3.4 Gate induced drain leakage 55
4.3.5 The variation of interface states and oxide trap charge after Stress 58
Chapter 5 CONCLUSION AND FUTURE WORKS 60
5.1 Conclusion 60
5.2 Future Work 61
REFERENCES 62

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