臺灣博碩士論文加值系統

電子產品技術的發展可說是日新月異的發展，而在可攜式電子產品中，電源管理系統也非常重要，其中低變動的穩壓性能及快速的負載暫態響應也是重要的考量。而在這個電子產品快速發展的時代，體積越來越小亦是市場上的趨勢，電源管理系統的面積也是電路設計的研究重點，本篇論文將針對這些性能去做探討。
本篇論文所提出的LDO架構使用T18製程實現，設計一個低壓降穩壓器，以穩壓器的基本原理做延伸擴展，研究如何大幅提升穩壓器對負載端提供電流的傳遞能力，使得穩壓器具有優異的暫態響應性能，且有效的降低功率電晶體(Mp)的面積，藉由提升電流傳遞能力、顯著的提升了穩壓器的工作速度，使得穩壓器有優異的負載暫態響應，在突升(Overshoot)、突降(Undershoot)、回復時間(Recovery Time)上得到改善、並在負載於重載(Full Load)時有穩定的輸出電壓(Vo)。
電路架構包含了兩個誤差放大器電路、電流鏡、動態偏壓電路、偏壓產生器、補償電容、以及多級導通電晶體所組成，並利用HSPICE等工具軟體來模擬調整電晶體至適當的尺寸，最後由LAKER來實現整體晶片，電路設計當輸入電壓在1.2V時 ，此穩壓器的輸出電壓能維持在1.0伏特，最大輸出負載電流為6mA，米勒補償電容為1.5pf。

The technology of electronic products develop rapidly. In the development of portable electronic products, the power management system is also becoming more and more important. The low change of regulator performance and fast load transient response are also important considerations. In this era of rapid development of electronic products, the volume getting smaller is needed in the market tendency, the area pf power management system is also important in circuit design. This thesis will discuss these considerations.
This thesis proposes a LDO regulator which has been implemented in TSMC T18 process technology. It shows how to significantly increase the regulator current transfer capacity, making the regulator have excellent transient response, effectively reducing the power transistor (Mp) area, enhancing the regulator's operating speed, having a good performance on overshoot, undershoot, recovery time, and has a stable output voltage at full load.
The circuit of the proposed LDO consists of two error amplifiers, a current mirror, a dynamic bias circuit, a bias generator, a compensation capacitor, and multi-stage pass transistor. The HSPICE tool is used to simulate and adjustment the pass transistors to the appropriate size. Finally the LAKER tool is used to achieve the layout of the whole chip of the proposed LDO. When the input voltage is given at 1.2V, the regulator's output voltage can be maintained at 1.0V. The maximum output load current of 6mA, the miller compensation capacitor is 1.5pf.

誌謝 i
摘要 ii
Abstract iii
目錄 v
圖表 ix
表格 xiv
第一章 緒論1
1.1 研究背景1
1.2 研究動機1
1.3 研究發展及流程 2
1.4 論文組織及架構 3
第二章 低壓降線性穩壓器工作原理以及重要參數之介紹 4
2.1 低壓降穩壓器介紹與基本工作原理 4
2.2 低壓降穩壓器的重要參數定義 5
2.2.1 輸入輸出電壓差(Dropout Voltage) 6
2.2.2 負載調節律(Load Regulation) 7
2.2.3 線性調節律(Line Regulation) 8
2.2.4 暫態響應(Transient Response) 9
2.2.5 靜態電流(Quiescent Current) 11
2.2.6 電流效率(Current Efficiency) 12
2.2.7 電源效率(Power Efficiency) 12
2.2.8 電源拒斥比(Power Suply Rejection Ratio) 13
2.2.9 輸出雜訊(Noise) 13
2.2.10 頻率響應(Frequency Response). 14
2.2.11 電壓精確度(Accuracy) 18
第三章 低壓降線性穩壓器的設計與模擬比較22
3.1 研究動機22
3.2 穩壓器電路的設計與想法22
3.2.1 誤差放大器(Error amplifier)工作原理23
3.2.2 動態偏壓技術(Dynamic biasing) 24
3.2.3 回授電路(Feedback Circuit) 25
3.3 二級導通電晶體架構 25
3.4 基體效應(Body Effect)調節架構 27
3.5 文獻回顧 29
3.6 架構設計 32
3.7 各級電路架構模擬與比較 34
3.7.1模擬想法 34
3.7.2暫態響應(TransientResponse) 36
3.7.2.1 暫態響應-固定Mp Size 36
3.7.2.2暫態響應-固定輸出電壓 42
3.7.3線性調節率(Line Regulation) 46
3.7.3.1 線性調節率-電源變化@1.1V~1.3V 46
3.7.3.2 線性調節率-電源變化@0~1.2V–啟動時間 47
3.7.3.3 線性調節率-電源變化@0V~1.37V-最低啟動電壓 48
3.7.4頻率響應(Frequency Response) 49
3.7.5電源拒斥比(Power Suply Rejection Ration) 54
第四章 電路模擬與實現 56
4.1 電路模擬-TSMCT18製程-Pre Simulation 56
4.1.1本篇穩壓器架構電路圖 56
4.1.2暫態響應(Transient Response)-負載調節(Load Regulation) 56
4.1.3暫態響應-線性調節(Line Regulation) 61
4.1.4頻率響應(Frequency Response) 63
4.1.5電源拒斥比(Power Suply Regection Ratio) 66
4.2 電路模擬-TSMCT18製程-Postsimulation 67
4.2.1 本論文電路圖 67
4.2.2 本論文晶片layout圖 67
4.2.3 暫態響應-負載調節(Load Regulation) 68
4.2.4 暫態響應-線性調節(Line Regulation) 72
4.2.5 頻率響應(Frequency Response) 74
4.2.6 電源拒斥比(Power Suply Regection Ratio) 77
第五章 結論與規格比較 78
5.1結論 78
5.2各低壓降線性穩壓器規格比較表 79
參考文獻 80

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