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研究生:楊旅皓
研究生(外文):Yang-Lu Hao
論文名稱:使用電子阻障層提升雙通道增強型氮化鋁鎵/氮化鎵高電子遷移率電晶體崩潰電壓
論文名稱(外文):Improving Breakdown Voltage for Enhancement-mode Double-Channel AIGaN/GaN HEMTs with Electron-blocking layers
指導教授:張彥華
指導教授(外文):CHANG, YANG-HUA
口試委員:張彥華劉啓忠賴志賢
口試委員(外文):CHANG, YANG-HUALIU, CHI-CHUNGLAI, CHIH HSIEN
口試日期:2017-07-20
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:105
語文別:中文
論文頁數:97
中文關鍵詞:高電子遷移率晶體崩潰電壓電子阻障層
外文關鍵詞:high electron mobility transistorsbreakdown voltageelectron-blocking layer
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摘要
本論文使用半導體模擬軟體Sentaurus TCAD來進行雙通道氮化鋁鎵/氮化鎵高電子遷移率電晶體的電性模擬與改良。氮化鋁鎵/氮化鎵高電子遷移率電晶體因為其氮化鋁鎵與氮化鎵之間的能隙差異,會在接面處形成量子井。在未加偏壓下,電子就會受極化效應的影響而集中到量子井中形成二維電子氣通道,故為空乏型元件。在電路應用中,空乏型元件必須給予閘極負偏壓才能關閉,這使得電路的複雜度增加,因此增強型氮化鋁鎵/氮化鎵高電子遷移率電晶體的開發是需要的。
設計增強型雙通道元件的困難之處在於必須同時空乏上下通道的電子,因此本研究結合了多種方法,包括調整掘入式閘極深度、氮化鋁鎵鋁莫耳比、p-GaN摻雜濃度,成功地設計出增強型結構。接著將增強型結構進行off- state 崩潰電壓的提升,加入電子阻障層(electron-blocking layers),並且改變電子阻障層厚度、鋁莫耳比優化改善元件之崩潰電壓(breakdown voltage, BV)。

關鍵字:高電子遷移率電晶體、崩潰電壓、電子阻障層。

ABSTRACT
In this thesis, simulation and improvement of double-channel AlGaN/GaN HEMTs by using Sentaurus TCAD is reported. Due to the energy gap difference between AlGaN and GaN, a quantum well is formed at the interface. Electrons are moved by the polarization effect and accumulated at the quantum well, forming 2DEG in the channel even when the gate bias is not applied. Therefore, the HEMTs become depletion mode. In circuit applications, depletion-mode transistors requires a negative supply voltage, which makes the circuit more complicate. As a result, development of enhancement-mode AlGaN/GaN HEMTs is highly desirable.
The challenge in designing an enhancement-mode double-channel HEMT is that it is much more difficult to deplete the electrons in the lower channel. In this work, a variety of techniques are integrated, including optimizing the depth of the recessed gate, the Al ratio in the AlGaN layer, and the doping concentration of the p-GaN region. Then an electron-blocking layer (EBL) structure is implemented and optimized to improve the breakdown voltage.


Keywords: high electron mobility transistors, breakdown voltage, electron-blocking layer (EBL).

目錄
摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第一章 緒論 1
1-1前言 1
1-2研究背景與研究目的 2
1-3論文架構 4
第二章 HEMTs基本原理與崩潰電壓 5
2-1 AlGaN/GaN HEMTs基本原理與元件種類 5
2-1-1異質接面材料極化效應 5
2-1-2 AlGaN層鋁濃度與厚度的影響 10
2-1-3 AlGaN/GaN HEMTs元件種類 12
2-2雙通道AlGaN/GaN HEMTs 13
2-3 AlGaN/GaN HEMTs基本原理與元件種類 15
2-3-1厚度較薄或鋁含量較低的氮化鋁鎵層 15
2-3-2氟化物電漿處理或氟離子佈植 15
2-3-3掘入式閘極 17
2-3-4氮化鋁鎵緩衝層 18
2-4提升崩潰電壓的方法 20
2-4-1閘極電場板AlGaN/GaN HEMTs 20
2-4-2閘極斜場板AlGaN/GaN HEMTs 22
2-4-3 AlGaN/GaN HEMTs P型摻雜 22
第三章 模擬物理模型介紹與AlGaN/GaN HEMTs元件模擬分析 24
3-1關於HEMTs物理模型簡介 24
3-1-1基本的電流電壓計算模型 25
3-1-2複合模型(recombination model) 28
3-1-3遷移率模型(mobility model) 28
3-1-4極化模型(polarization model) 30
3-1-5邊界條件(polarization model) 31
3-1-6數值方法(Numerical Method) 32
3-2模擬與量測值匹配 33
3-2-1 單通道AlGaN/GaN HEMTs結構 33
3-2-2建立元件網格 34
3-2-3極化效應模擬 35
3-2-4測量值與模擬匹配結果 38
第四章 結果與討論 40
4-1 AlGaN/GaN雙通道元件結構與崩潰電壓 41
4-1-1雙通道元件結構 41
4-1-2元件之崩潰電壓 42
4-1-3將空乏型元件改為增強型 43
4-2加入電子阻障層 44
4-3提升元件崩潰電壓 45
4-3-1電子阻障層鋁莫耳比對轉導峰值的影響 46
4-3-2提升崩潰電壓 59
第五章 結論 77
參考文獻 78

表目錄
表1-1 GaN與其他半導體材料特性比較[1] 2
表2-1 AlxGa1-xN材料與GaN與AlN材料特性[9] 6
表2-2 氮化物材料極化參數[10] 7
表2-3 氮化物材料彈性係數與壓電係數表[11] 8
表3-1 Masetti Model參數表[35] 29
表3-2 模擬與Paper公式計算之極化向量值比較[36] 38
表4-1 選出三個崩潰電壓最佳的增強型結構 44
表4-2 閘極掘入深度 5 nm 、p-GaN參雜濃度4e18改善崩潰電壓 74
表4-3 閘極掘入深度 10 nm 、p-GaN參雜濃度1e19改善崩潰電壓 74
表4-4 閘極掘入深度 15 nm 、p-GaN參雜濃度4e19改善崩潰電壓 75
表4-5 電子阻障層5 nm比較閘極掘入深度5 nm、10 nm、15 nm改善崩潰電 76

圖目錄
圖1-1 GaN與AlGaN/GaN 異質接面造就的高電子傳輸特性[2] 3
圖2-1 GaN與AlN材料的六方最密堆積結構(Hexagonal close-packed, hcp) [6] 5
圖2-2 GaN材料之Ga(Al)-face與N-face[8] 6
圖2-3磊晶層應變產生壓電極化向量(PPE) 8
圖2-4 鋁莫耳比含量與電子密度關係圖[10] 10
圖2-5 氮化鋁鎵層厚度與電子密度關係圖[11] 11
圖2-6 AlGaN/AlN/GaN異質接面結構示意圖[14] 12
圖2-7 異質接面AlGaN/GaN HEMTs結構圖[15] 12
圖2-8 雙通道 AlGaN/GaN/ HEMTs結構圖[14] 13
圖2-9 (a)單通道與(b)雙通道結構之導電帶及電子密度分佈圖[15] 14
圖2-10 雙通道HEMT 之轉導曲線[16] 14
圖2-11 掘入式閘極HEMTs 結構[17] 16
圖2-12 掘入式閘極MISHEMT 結構[19] 16
圖2-13 氟離子佈植於閘極下方可空乏通道電子[21] 17
圖2-14 氟離子佈植與CF4 電漿蝕刻後之ID-VG與轉導曲線[23] 18
圖2-15 (a)氮化鎵緩衝層與(b)氮化鋁鎵緩衝層結構[24] 19
圖2-16 氮化鎵緩衝層與氮化鋁鎵緩衝層之(a)導電帶及(b)電子密度分佈[25] 19
圖2-17 改用氮化鋁鎵緩衝層對臨界電壓及轉導曲線的影響[27] 20
圖2-18 AlGaN/GaN HEMTs閘極電場板[28] 21
圖2-19 沿著通道2DEG的電場模擬分布圖[28] 21
圖2-20 (a)AlGaN/GaN HEMT閘極斜場板截面圖(b)閘極斜場板SEM截面[29] 22
圖2-21 傳統元件與摻雜元件截面示意圖[34] 23
圖2-22 模擬截止狀態閘截邊緣的電位分佈與電場方向[34] 23
圖3-1 單通道AlGaN/GaN HEMTs結構 34
圖3-2 元件整體網格 34
圖3-3 局部網格放大 35
圖3-4 網格樞密對極化電荷的影響[36] 35
圖3-5 元件縱向切線下不同材料層的極化向量值[36] 36
圖3-6 材料層中極化電荷的分佈狀況[36] 37
圖3-7 材料層與接面的極化電荷密度(cm^(-2))[36] 37
圖3-8 IDs-VDs電流電壓關係圖(VG = 0 V)[36] 39
圖3-9 IDs-VDs電流電壓關係圖(VD = 0.5 V)[36] 39
圖4-1 改為增強型結構流程圖 40
圖4-2 提升崩潰電壓流程圖 41
圖4-3 AlGaN/GaN雙通道元件結構(原結構) 42
圖4-4 HEMTs元件結構,改變閘極掘入深度三種搭配, 以及搭配不同鋁莫耳比三種,共九種結構 43
圖4-5 電子阻障層位置圖 45
圖4-6 電子阻障層(EBL)厚度中分三層結構總厚度及定義第一層p-AlXGa1-XN鋁莫爾比為(X)、第三層p-AlYGa1-YN鋁莫爾比為(Y) 45
圖4-7 電子阻障層5 nm、p-GaN摻雜濃度4e18固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 46
圖4-8 電子阻障層5 nm、p-GaN摻雜濃度4e18固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 47
圖4-9 電子阻障層10 nm、p-GaN摻雜濃度4e18固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 48
圖4-10 電子阻障層10 nm、p-GaN摻雜濃度4e18固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 48
圖4-11 電子阻障層15 nm、p-GaN摻雜濃度4e18固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 49
圖4-12 電子阻障層15 nm、p-GaN摻雜濃度4e18固定第三層鋁莫耳比Y改變第
一層鋁莫耳比X的Gm-VGS圖 50
圖4-13 電子阻障層5 nm、p-GaN摻雜濃度1e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 51
圖4-14 電子阻障層5 nm、p-GaN摻雜濃度1e19固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 51
圖4-15 電子阻障層10 nm、p-GaN摻雜濃度1e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 52
圖4-16 電子阻障層10 nm、p-GaN摻雜濃度1e19固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 53
圖4-17 電子阻障層15 nm、p-GaN摻雜濃度1e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 54
圖4-18 電子阻障層15 nm、p-GaN摻雜濃度1e19固定第三層鋁莫耳比Y改變第
一層鋁莫耳比X的Gm-VGS圖 54
圖4-19 電子阻障層5 nm、p-GaN摻雜濃度4e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 55
圖4-20 電子阻障層5 nm、p-GaN摻雜濃度4e19固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 56
圖4-21 電子阻障層10 nm、p-GaN摻雜濃度4e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 57
圖4-22 電子阻障層10 nm、p-GaN摻雜濃度4e19固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 57
圖4-23 電子阻障層15 nm、p-GaN摻雜濃度4e19固定第一層鋁莫耳比X改變第三層鋁莫耳比Y的Gm-VGS圖 58
圖4-24 電子阻障層15 nm、p-GaN摻雜濃度4e19固定第三層鋁莫耳比Y改變第一層鋁莫耳比X的Gm-VGS圖 59
圖4-25固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰
值( VG = 0V、VD = 20V ) 60
圖4-26 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰
值( VG = 0V、VD = 40V ) 61
圖4-27 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 15V ) 62
圖4-28 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD = 25V ) 62
圖4-29 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 15V ) 63
圖4-30 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD =20 V ) 64
圖4-31 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 13V ) 65
圖4-32 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD = 20V ) 65
圖4-33 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 13V ) 66
圖4-34 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD = 19V ) 67
圖4-35 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 5V ) 68
圖4-36 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD =10V ) 68
圖4-37 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 16V ) 69
圖4-38 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD = 24V ) 70
圖4-39 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 8V ) 71
圖4-40 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD = 14V ) 71
圖4-41 固定上層EBL鋁莫耳比(X),改變下層EBL鋁莫耳比(Y)上通道電場峰值( VG = 0V、VD = 3V ) 72
圖4-42 固定下層EBL鋁莫耳比(Y),改變上層EBL鋁莫耳比(X)上通道電場峰值( VG = 0V、VD =8 V ) 73

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[35] The introduction of sentaurus TCAD –S-Device, Published by Synopsys Sentaurus Device.

[36] 林佳億,2014,雙通道氮化鋁鎵/氮化鎵高電子遷移率電晶體之線性度提升
,國立雲林科技大學,碩士論文。

[37] Ya-Ju Lee1, Yung-Chi Yao, Chun-Ying Huang, Tai-Yuan Lin, Li-Lien Cheng, Ching-Yun Liu, Mei-Tan Wang and Jung-Min Hwang, “ High breakdown voltage in AlGaN/GaN HEMTs using AlGaN/GaN/AlGaN quantum-well electron-blocking layers, ” Lee et al. Nanoscale Research Letters 2014, 9:433.

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