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研究生:宋長恩
研究生(外文):SUNG, CHANG-EN
論文名稱:基於降低開關元件數量的單相多階變流器之研製
論文名稱(外文):Single Phase Multilevel Inverters Based on Reduced Number of Switch Count
指導教授:葉增雄
指導教授(外文):YEH, TZENG-SHONG
口試委員:鄧人豪卓明遠
口試委員(外文):TENG, JEN-HAOCHO, MING-YUAN
口試日期:2018-07-03
學位類別:碩士
校院名稱:國立高雄應用科技大學
系所名稱:電機工程系博碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:115
中文關鍵詞:多階變流器降低開關元件數量現場可程式邏輯閘陣列
外文關鍵詞:Multilevel invertersreduced number of switch countFPGA
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本論文探討基於降低開關元件數量的不同架構新型多階變流器,與傳統的多階變流器架構相較,當達到特定的輸出電壓位階時,新型的多階變流器所需之功率元件數目較少,此可降低裝置空間及設備成本。文中探討四種新型變流器,詳細敘述其電路架構及切換模式,並且比較其差異性,其後利用MATLAB/Simulink模擬軟體針對四種新型變流器進行模擬與分析,探討輸出電壓波形、諧波頻譜及開關耐壓,最後以ALTERA公司的Quartus II軟體設計開關激發信號,隨後燒錄至DE2-115 FPGA開發板中,再以MOSFET組成之電路進行實作驗證,驗證模擬與實際測量之結果。
This thesis investigates different topologies of single phase multilevel inverters based on reduced number of switch count. In comparing with other conventional multilevel inverters, the benefit of use small number of devices to obtain the same voltage level is validated. New multilevel inverters can also reduce the installation space and cost. Among the new multilevel inverters, four new inverters are discussed, and their circuit topology and switching modes are described in detail, and then compare the differences. Simulation results from MATLAB/Simulink are used to validate the theoretical analysis. Finally, the ALTERA’s software Quartus II is used to design the switch excitation signals, then the code is downloaded to a FPGA board DE2-115. The MOSFET-based new multilevel inverters are implemented and experimental results verify the feasibility.
目錄
中文摘要 i
英文摘要 ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究背景與動機 1
1.2 相關文獻回顧 2
1.3 論文架構概述 3
第二章 單相多階變流器 4
2.1 傳統變流器 5
2.2 基於降低開關元件數量之變流器 8
2.2.1 新型變流器1 8
2.2.2 新型變流器2 12
2.2.3 新型變流器3 16
2.2.4 新型變流器4 22
2.3 不同架構之比較 27
第三章 基於降低開關元件數量變流器之調變技術 30
3.1 正弦脈波寬度調變法 31
3.2 多載波移相脈寬調變法 32
3.3 多載波移階脈寬調變法 33
第四章 以MATLAB模擬單相多階變流器 36
4.1 多載波移相脈寬調變法之模擬分析與討論 36
4.2 多載波移階脈寬調變法之模擬分析與討論 41
4.2.1 APOD(交替相位相反配置)調變法 41
4.2.2 POD(相位相反配置)調變法 45
4.2.3 IPD(同相配置)調變法 49
4.3 不同變流器架構之模擬比較 55
4.4 非對稱的單相多階變流器 64
4.4.1 非對稱型之新型變流器1 64
4.4.2 非對稱型之新型變流器2 69
第五章 以FPGA實作單相多階變流器之多載波脈寬調變法 75
5.1 多載波移階脈寬調變法之設計 76
5.2 單相多階變流器之實作結果 80
5.2.1 APOD調變法 81
5.2.2 POD調變法 83
5.2.3 IPD調變法 85
5.3 不同變流器架構之實作比較 87
5.3.1 新型變流器1之耐壓 87
5.3.2 新型變流器2之耐壓 90
5.4 非對稱型單相多階變流器之實作結果 93
第六章 結論與未來展望 98
6.1 結論 98
6.2 未來展望 100
參考文獻 101

[1]Bin Wu, High-Power Converters and AC Drives, IEEE Press, March 2006.
[2]L. S. Lim, N. J. Ku and D. S. Hyun, "A Simplified Space Vector PWM Scheme for N-Level NPC Inverter Based on Two-Level Space-Vector PWM," Vehicle Power and Propulsion Conference. (VPPC) , pp.1-6, 2014.
[3]D. Floricau, G. Gateau, and T. A. Meynard, “New Multilevel Flying Capacitor Inverters with Coupled-Inductors,” in Proc. 13th Int. Optimization of Electrical and Electronic Equipment Conf. (OPTIM), pp. 764–769, May. 2012.
[4]K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu, and S. Jain, “Multilevel inverter topologies with reduced device count: A review,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 135–151, Jan. 2016.
[5]J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. C. Portillo, M. A. M. Prats, and M. A. Perez, “Multilevel converters: An enabling technology for high-power applications,” in Proc. IEEE, vol. 97, no. 11, pp. 1786–1817, Nov. 2009.
[6]K. K. Gupta, L. Kumar and S. Jain,“A New Seven-Level Hybrid Inverter,” IEEE International Conference on Power Electronics, Drives and Energy Systems, pp. 16-19, Dec. 2012.
[7]K. K. Gupta and S. Jain, “A novel multilevel inverter based on switched DC sources,” IEEE Trans. Ind. Electron., vol. 61, no. 7, pp. 3269–3278, Jul. 2014.
[8]A. Ajami, M. R. J. Oskuee, M. T. Khosroshahi, and A. O. Mokhberdoran, “Cascade-multi-cell multilevel converter with reduced number of switches,” IET Power Electron., vol. 7, no. 3, pp. 552–558, Apr. 2014.
[9]M. Farhadi and E. Babaei, “Cross-switched multilevel inverter: An innovative topology,” IET Trans. Power Electron., vol. 6, no. 4, pp. 642–651, Apr. 2013.
[10]S. Jain and K. K. Gupta, “Multilevel inverter topology based on series connected switched sources,” IET Power Electron., vol. 6, no. 1, pp. 164–174, Jan. 2013.
[11]N. Prabaharan and K. Palanisamy, “Comparative analysis of symmetric and asymmetric reduced switch MLI topologies using unipolar pulse width modulation strategies,” IET Power Electron., vol. 19, no. 15, pp. 2808-2823, Dec. 2016.
[12]O. Husev, R. Strzelecki, F. Blaabjerg, V. Chopyk, and D. Vinnikov, “Novel family of single-phase modified impedance-source buck-boost multilevel inverters with reduced switch count,” IEEE Trans. Power Electron., vol. 31, no. 11, pp. 7580–7591, Nov. 2016.
[13]M. Jayabalan, B. Jeevarathinam, and T. Sandirasegarane “Reduced switch count pulse width modulated multilevel inverter,” IET Power Electron., vol. 10, no. 1,pp.10-17, Jan. 2017.
[14]M. R. Subbamma, T. M. Prasad, and V. Madhusudhan, “Comparison of single-phase cascaded and multilevel dc link inverter with pulse width modulation control methods,” International Conference on Sustainable Energy and Intelligent Systems (SEISCON), pp. 229-235, Jul. 2011.
[15]E. Babaei, S. Laali, and Z. Bayat, “A single-phase cascaded multilevel inverter based on a new basic unit with reduced number of power switches,” IEEE Trans. Ind. Electron., vol. 62, no. 2, pp. 922-929, Feb. 2015.
[16]E. Babaei, M. A. Hosseinzadeh, M. Sarbanzadeh, and C. Cecati, “A new basic unit for cascaded multilevel inverters with reduced number of power electronic devices,” in Proc. PEDSTC, 2016, Tehran, Iran, pp. 197-202, Feb. 2016.
[17]R. S. Alishah, S. H. Hosseini, E. Babaei, and M. Sabahi, “A new general multilevel converter topology based on cascaded connection of sub-multilevel units with reduced switching components, dc sources, and blocked voltage by switches,” IEEE Trans. Ind. Electron., vol. 63, no. 11, pp. 7157–7164, Nov. 2016.
[18]M. T. Khosroshahi “Crisscross cascade multilevel inverter with reduction in number of components,” IET Power Electron., pp. 1519–1526, Jul. 2014,.
[19]S. P. Gautam, L. Kumar, and S. Gupta, “Hybrid topology of symmetrical multilevel inverter using less number of devices,” IET Power Electron., vol. 8, no. 11, pp. 2125–2135, Nov. 2015.
[20]廖裕評、陸瑞強,“系統晶片設計-使用Quartus II”,全華圖書股份有限公司,2012年5月。

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