由於近年來半導體製程快速發展，提升了整體電路的操作速度，消費性電子產品顯示畫質也變得越來越高。由較早期的解析度480P(640×480)至到目前主流畫質Full HD 1080P(1920×1080)，加上目前行動裝置與電視之間影音串流應用快速發展，因此顯示器的高速介面電路必須達到更高的傳輸速率來滿足高畫質的影音傳輸。為了達到下個世代高解析度Ultra HD 4K2K(3840×2160)的規格，應用在大型顯示器的高速介面電路由早期的多點傳輸變成點對點傳輸來達到更高速、低功耗的特性。本論文之設計主要針對大型顯示器高速介面中的嵌入式時脈差分訊號為目標，並透過自適性等化器結合1/3-速率取樣方式來實現時脈與資料回復電路。
本論文第一部分所設計實現的3-Gb/s具有振幅控制迴路類比等化器可以補償大尺寸顯示器在1.5-GHz時24-dB的通道損失。為了解決輸入、輸出限幅放大器振幅不同，以及高頻補償空間受到低頻補償而造成壓縮的問題，本論文採用具有振幅控制迴路的系統架構。本晶片以聯電0.18-μm 1P6M CMOS製程來實現，在工作電壓為1.8-V時，其功率消耗為27-mW，而核心部分面積為0.12-(mm)^2，輸出峰對峰值抖動為0.256-UI。
本論文第二部分所實現的3-Gb/s具自適性等化器之時脈與資料回復電路，為了達到高速、低功耗、低抖動的特性，我們提出1/3-速率取樣技術，除此之外整個系統架構採用全差動的方式來完成。本晶片以聯電0.18-μm 1P6M CMOS製程來實現，在工作電壓為1.8-V時，取樣速率為1-Gb/s時，其功率消耗為112-mW，而核心部分面積為0.36-(mm)^2，回復時脈峰對峰值抖動為5.07-ps，並列3組輸出的回復資料峰對峰值抖動分別為5.31、4.75、4.23-ps。

Due to the rapid development of semiconductor process in recent years, the operating speed of the overall circuit increases progressively, and the display quality of consumer electronics, too. The video streaming applications develop rapidly between mobile devices and TVs, from the early resolution 480P(640×480) to the current mainstream Full HD 1080P(1920×1080), resulting in that, the high-speed display interface must achieve a higher transmission rate to satisfy the high-definition video. In order to achieve the next generation Ultra HD 4K2K(3840×2160) specification, the high-speed interface used in large display panel have replaced from early multi-drop systems to point-to-point systems for higher speed and lower power consumption.
In the first part, this thesis proposes a 3-Gb/s equalizer with adaptive swing controller that compensates for the large display panel channel loss of 24-dB at 1.5GHz. In order to solve the different amplitude between input and output of limiting amplifier, and tradeoff between high-frequency and low-frequency compensation issue, we use adaptive swing controller technique. The test chip was implemented in UMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.8-V with 27-mW. The core area is 0.12-(mm)^2, and output peak-to-peak jitter is 0.256-UI.
In the second part, the thesis proposes a 3-Gb/s clock and data recovery with adaptive equalizer. In order to achieve high speed, lower power consumption and jitter, we propose a 1/3-rate sampling technique, and the entire system architecture is made up by fully differential structure. The test chip was implemented in UMC 0.18-μm 1P6M CMOS technology. It works at power supply 1.8-V and sampling rate is 1Gb/s with 112-mW. The core area is 0.36-(mm)^2, and peak-to-peak jitter of recovery clock is 5.07-ps, and recovery data of 1-Gb/s peak-to-peak jitter is 5.31、4.75、4.23-ps, respectively.

致謝 i
摘要 ii
Abstract iii
目錄 v
圖目錄 viii
表目錄 xiv
第一章 緒論 1
1.1 論文動機 1
1.2 大尺寸顯示器的高速介面簡介 2
1.3 時脈資料回復電路的抖動參數 6
1.3.1 抖動產生 6
1.3.2 抖動轉移函數 6
1.3.3 抖動峰值 7
1.3.4 抖動容忍度 9
1.4 論文架構 10
第二章 自適性等化器電路架構 11
2.1 自適性等化器的發展 11
2.2 傳統類比等化器電路架構 12
2.2.1 頻譜平衡技術的電路架構 12
2.2.2 傳統單迴路控制的電路架構 13
2.2.3 雙迴路控制的電路架構 14
2.2.4 振幅迴路控制的電路架構 15
2.3 高頻補償電路 16
2.3.1 Cherry-Hopper放大器 16
2.3.2 源級退化的技巧 19
2.3.3 增加零點的技巧 20
2.3.4 增加被動高通網路的技巧 22
2.3.5 fT倍頻電路 24
2.3.6 正回授的技巧 25
第三章 具有振幅控制迴路類比等化器的設計與實現 27
3.1 類比等化器電路架構 27
3.2 類比等化器的子電路介紹 30
3.2.1 高頻補償電路 30
3.2.2 帶通濾波器 38
3.2.3 整流器與誤差放大器 39
3.2.4 限幅放大器 41
3.3 類比等化器的模擬結果 42
3.4 類比等化器的晶片佈局與量測 47
第四章 時脈資料回復電路 53
4.1 時脈與資料回復電路簡介 53
4.1.1 串列傳輸與並列傳輸 54
4.1.2 資料形式 55
4.2 相位偵測器簡介 56
4.2.1 線性相位偵測器 57
4.2.2 二位元相位偵測器 61
4.3 取樣速率 63
4.4 時脈與資料回復電路架構 64
4.4.1 以鎖相迴路為基底之時脈回復電路 64
4.4.2 以延遲鎖定迴路為基底之時脈資料回復電路 68
4.4.3 結合鎖相迴路與延遲鎖定迴路之時脈資料回復電路 69
4.4.4 以相位內插為基底之時脈資料回復電路 70
4.4.5 以超取樣為基底之時脈資料回復電路 71
第五章 具有1/3-速率時脈資料回復電路的設計與實現 73
5.1 時脈資料回復電路的系統架構與迴路分析 73
5.2 系統參數設計與行為模擬 79
5.3 時脈資料回復電路的子電路介紹 82
5.3.1 差動控制環形振盪器 82
5.3.2 相位頻率偵測器 84
5.3.3 相位偵測器 86
5.3.4 除頻器 90
5.3.5 充電泵 91
5.3.6 訊號選擇器 93
5.3.7 鎖定偵測器 94
5.4 時脈資料回復電路的模擬結果 95
5.5 時脈資料回復電路的晶片佈局與量測 99
第六章 結論 107
參考文獻 108

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