臺灣博碩士論文加值系統

當負電容電晶體（Negative Capacitance FET, NC-FET）的通道材料使用二維材料，例如：黑磷和二硫化鉬，可以解決CMOS元件持續微縮的問題，電晶體的功率消耗分別為靜態功率消耗和動態功率消耗，以上兩種功率消耗都與操作電壓VDD有關，因此為了節省電晶體的功率消耗的問題，則操作電壓VDD必須降低。在室溫下，MOSFET的物理極限的次臨界擺幅（Subthreshold Swing, S. S.）約為60 mV/decade，因此限制了開關特性，為了突破這個物理極限，近年來有許多學者提出把鐵電材料當介電質層，提出具負電容效應的鐵電材料串聯堆疊在傳統電晶體的閘極上方來改善此限制。
本論文研究中建立黑磷和二硫化鉬這兩種材料的參數檔，然後使用Sentaurus TCAD模擬軟體來進行黑磷電晶體和二硫化鉬電晶體的模擬研究，且在研究過程中也進行單層和三層二維材料的比較；之後使用MATLAB軟體建立一個負電容電壓計算程式，然而把負電容電壓計算程式與Sentaurus TCAD模擬軟體結合在一起，因此可以模擬出元件加入負電容效應後新的ID-VGS，這裡鐵電材料是HfZrO2且研究方法已經考慮了在不同材料層之間的電荷連續性問題。
最後把黑磷電晶體和二硫化鉬電晶體進行電流開關比（On/Off Ratio）、汲極導致位障降低（Drain-Induced Barrier Lowering, DIBL）和次臨界擺幅（Subthreshold Swing, S. S.）比較，在電流開關比和次臨界擺幅方面是黑磷電晶體比二硫化鉬電晶體還要好，則在汲極導致位障降低方面是三層黑磷電晶體比單層黑磷電晶體還要好。

When two-dimensional materials, e.g. black phosphorus and molybdenum disulfide, are used for channel materials of NC-FET, the scaling problem of CMOS device could be solved. The power consumption of transistors is divided into static power consumption and dynamic power consumption. Both types of power consumption are related to operating voltage VDD. In this case, operating voltage VDD should be reduced to save the power consumption of transistors. Under room temperature, the subthreshold swing （S. S.）of the physical limit of MOSFET is about 60 mV/decade to restrict the on/off characteristics. In order to break through such physical limits, a lot of researchers proposed to use ferroelectric materials as the dielectric layer to improve the limit by stacking ferroelectric materials, which present negative capacitance effect, in series on the gate of traditional transistors.
The parameters of black phosphorus and molybdenum disulfide are established in this study, and Sentaurus TCAD simulation software is used for simulating black phosphorus transistors and molybdenum disulfide transistors; in the process, single-layer and three-layer two-dimensional materials are also compared. MATLAB is further used for establishing a negative capacitance voltage calculation program for combining with Sentaurus TCAD to simulate the new ID-VGS after negative capacitance effect is added to the transistor. HfZrO2 is the ferroelectric material, and the charge continuity between different layers are taken into account in the research method.
Finally, black phosphorus transistors and molybdenum disulfide transistors are compared the current on/off ratio, drain-induced barrier lowering （DIBL）, and subthreshold swing （S. S.）. In terms of current on/off ratio and subthreshold swing, black phosphorus transistors outperform molybdenum disulfide transistors. In regard to drain-induced barrier lowering, three-layer black phosphorus transistors appear better performance than single-layer black phosphorus transistor.

Publication List i
誌謝辭 ii
中文摘要 iii
Abstract iv
目錄 vi
圖目錄 viii
表目錄 xv
第一章 緒論 1
第二章 材料與負電容理論介紹 4
2.1 材料特性 4
2.2 HfZrO2材料 6
2.3 二維材料 7
2.3.1 二硫化鉬 7
2.3.2 黑磷 8
2.4 負電容 9
2.4.1 負電容理論 9
2.4.2 負電容電壓放大理論 12
2.4.3 Landau-Khalatnikov Model 14
第三章 文獻回顧 15
第四章 研究方法 32
4.1 模擬流程 32
4.2 建立負電容電壓計算程式 33
4.3 建立單層和三層的二硫化鉬參數檔 35
4.4 建立單層和三層的黑磷參數檔 37
第五章 研究結果 39
5.1 負電容電壓計算程式驗證 39
5.2 MoS2 FET和NC-MoS2 FET的模擬結果 40
5.2.1 Gate Length為5.9 nm 40
5.2.2 Gate Length為15 nm 53
5.3 BPFET和NC-BPFET的模擬結果 60
5.4 MoS2 FET和BPFET的模擬結果比較 68
第六章 結論 71
第七章 未來工作 72
參考文獻 73

[1]International Technology Roadmap for Semiconductors (ITRS) Roadmap, 2009.
[2]S. Salahuddin and S. Datta, "Can the Subthreshold Swing in a Classical FET be Lowered Below 60 mV/decade?," IEDM Tech. Dig., pp. 693-696, 2008.
[3]G. A. Salvatore, D. Bouvet and A. M. Ionescu, "Demonstration of Subthrehold Swing Smaller Than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack," IEDM Tech. Dig., pp. 167-170, 2008.
[4]A. Rusu, G. A. Salvatore, D. Jiménez and A. M. Ionescu, "Metal-Ferroelectric-Metal-Oxide-Semiconductor Field Effect Transistor with Sub-60mV/decade Subthreshold Swing and Internal Voltage Amplification," IEDM Tech. Dig., pp. 395-398, 2010.
[5]Kittel and Charles, Introduction to Solid State Physics, 7th ed.: Wiley, 1996.
[6]http://www.itrc.narl.org.tw/Publication/Newsletter/no68/p10.php
[7]J. Müller, T. S. Böscke, U. Schröder, S. Mueller, D. Bräuhaus, U. Böttger, L. Frey and T. Mikolajick, "Ferroelectricity in Simple Binary ZrO2 and HfO2," Nano Lett., vol. 12, pp. 4318−4323, 2012.
[8]M.H. Lee, Y.-T. Wei, C. Liu, J.-J. Huang, M. Tang, Y.-L. Chueh, K.-Y. Chu, M.-J. Chen, H.-Y. Lee, Y.-S. Chen, L.-H. Lee and M.-J. Tsai, "Ferroelectricity of HfZrO2 in Energy Landscape With Surface Potential Gain for Low-Power Steep-Slope Transistors," IEEE Journal of the Electron Devices Society, vol. 3, pp. 377-381, 2015.
[9]L. K. Li, Y. J. Yu, G. J. Ye, Q. Q. Ge, X. D. Ou, H. Wu, D. L. Feng, X. H. Chen and Y. B. Zhang, "Black Phosphorus Field-effect Transistors," Nature Nanotech., vol. 9, pp. 372-377, 2014.
[10]X. Liu, K.-W. Ang, W. Yu, J. He, X. Feng, Q. Liu, H. Jiang, D. Tang, J. Wen, Y. Lu, W. Liu, P. Cao, S. Han, J. Wu, W. Liu, X. Wang, D. Zhu and Z. He, "Black Phosphorus Based Field Effect Transistors with Simultaneously Achieved Near Ideal Subthreshold Swing and High Hole Mobility at Room Temperature," Scientific Reports, vol. 6, pp. 24920-1-24920-8, 2016.
[11]劉謙, 使用鐵電負電容效應之低電壓超陡峭斜率電晶體模型及設計, 碩士論文, Ed. 台北: 國立台灣師範大學光電科技研究所, 2015.
[12]L. D. Landau, and I. M. Khalatnikov, "On the Anomalous Absorption of Sound Near a Second Order Phase Transition Point," Dokl. Akad. Nauk, vol. 96, pp. 469-472, 1954.
[13]V. C. Lo, "Simulation of Thickness Effect in Thin Ferroelectric Films Using Landau-Khalatnikov Theory," J.Appl. phys., vol. 94, pp. 3353-3359, 2003.
[14]W. Zhang and K. Bhattacharya, "A Computational Model of Ferroelectric Domains. Part I: Model Formulation and Domain Switching," Acta Materialia, vol. 53, pp. 185-198, 2005.
[15]D. Jiménez, E. Miranda and A. Godoy, "Analytic Model for the Surface Potential and Drain Current in Negative Capacitance Field-Effect Transistors," IEEE Trans. on Electron Device, vol. 57, pp. 2405-2409, 2010.
[16]A. I. Khan, C. W. Yeung, C. Hu and S. Salahuddin, "Ferroelectric Negative Capacitance MOSFET: Capacitance Tuning & Antiferroelectric Operation," IEDM Tech. Dig., pp. 255-258, 2011.
[17]C. W. Yeung, A. I. Khan, A. Sarker, S. Salahuddin and C. Hu, "Low Power Negative Capacitance FETs for Future Quantum-Well Body Technology," VLSI-TSA, pp. 179-180, 2013.
[18]K.-S. Li, P.-G. Chen, T.-Y. Lai, C.-H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, M.-C. Chen, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S. Salahuddin and Chenming Hu, "Sub-60mV-Swing Negative-Capacitance FinFET without Hysteresis," IEDM, pp. 22.6.1-22.6.4, 2015.
[19]C. Liu, P.-G. Chen, M.-J. Xie, S.-N. Liu, J.-W. Lee, S.-J. Huang, S. Liu, Y.-S. Chen, H.-Y. Lee, M.-H. Liao, P.-S. Chen and M.-H. Lee, "Simulation-Based Study of Negative-Capacitance Double-Gate Tunnel Field-Effect Transistor with Ferroelectric Gate Stack," Japanese Journal of Applied Physics, vol. 55, pp. 04EB08-1-04EB08-4, 2016.
[20]H. Ota, T. Ikegami, J. Hattori, K. Fukuda, S. Migita and Akira Toriumi, "Fully Coupled 3-D Device Simulation of Negative Capacitance FinFETs for Sub 10 nm Integration," International Electron Devices Meeting（IEDM）, pp. 12.4.1-12.4.4, 2016.
[21]F. Liu, Y. Zhou, Y. Wang, X. Liu, J. Wang and H. Guo, "Negative Capacitance Transistors with Monolayer Black Phosphorus," Quantum Materials, pp. 1-6, 2016.
[22]H. Ota, K. Fukuda, T. Ikegami, J. Hattori, H. Asai, S. Migita and A. Toriumi, "Perspective of Negative Capacitance FinFETs Investigated by Transient TCAD Simulation," International Electron Devices Meeting (IEDM), pp. 15.2.1-15.2.4, 2017.
[23]W.-X. You and P. Su, "Design Space Exploration Considering Back-Gate Biasing Effects for 2D Negative-Capacitance Field-Effect Transistors," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 64, pp. 3476-3481, 2017.
[24]V. P.-H. Hu, P.-C. Chiu, A. B. Sachid and C. Hu, "Negative Capacitance Enables FinFET and FDSOI Scaling to 2 nm Node," IEEE International Electron Devices Meeting (IEDM), pp. 23.1.1-23.1.4, 2017.
[25]V. P.-H. Hu and P.-C. Chiu, "Analysis of Switching Characteristics for Negative Capacitance Ultra-Thin-Body Germanium-on-Insulator MOSFETs," Japanese Journal of Applied Physics, vol. 57, pp. 04FD02-1-04FD02-5, 2018.
[26]Chang-Hung Yu, Pin Su and Ching-Te Chuang, "Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs," IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 64, pp. 2445-2451, 2017.