中值濾波器(Median Filter)常用在影像處理，主要用來消除胡椒鹽雜訊，目前常見的中值濾波器基於字級(word-level)的架構來設計，但該電路只適用在固定的資料寬度，缺乏彈性，當資料的寬度有所改變，架構往往必須重新設計，若資料寬度變長時，面積方面會大幅增加，效能則方面則會下降。
比較好的方式是使用位元級(bit-level)架構，透過串接方式可解決資料寬度變長時造成效能下降的問題。位元級的架構根據局部的位元長度做判斷，使用較少的資料暫存器與中值暫存器完成運算，藉此達到低成本高效能之目標。在此論文中，我們改善現有的位元級硬體架構，使用計數器(Counter)與省去比較電路(Comparator)，在計算速度不變的前提下，降低面積和功率消耗。
設計的硬體架構透過Verilog HDL來描述電路行為，使用Synopsys Design Compiler合成電路，製程為TSMC 90nm標準元件庫。實驗結果表示本論文設計的架構，當電路操作頻率在2000MHz下，與現有8位元架構相比面積方面減少16.78%，功耗方面減少28.66%，操作頻率在1666MHz下，16位元架構下面積方面減少15.11%，功耗方面減少28.33%。

A median filter is a widely used circuit in image processing, and it is mainly used to remove salt-and-pepper noise. Word-level architecture is a common way to design the median filter, but this architecture can only be applied to a fixed input data width and lacks flexibility. When the input data width changes, this architecture must be redesigned. If the data width becomes larger, this architecture requires larger area, while its performance is reduced.
A better way to design the median filter is to use bit-level cascaded architecture. The bit-level median filter is a pipelined architecture which is composed several partial-median filters. When the data length increases, the architecture only adds partial-median filters to increase pipeline stages. The operation frequency is not affected.
In this study, we use counters to replace accumulations and remove comparators to improve the bit-level architecture. To achieve low area and power consumption while maintain the operation speed. The proposed design is implemented in Verilog HDL and synthesized by Synopsys Design Compiler with TSMC 90mn library. Compared with the state-of-the-art median filter architecture. the area is reduced by 16.78%, and the power consumption is reduced by 28.66% in the 8-bit architecture when the operating frequency is 2000MHz. In the 16-bit architecture, the area is reduced by 15.11%, and the power consumption is reduced by 28.33% when the operating frequency is 1666MHz.

摘要 i
Abstract ii
誌謝 iii
Contents iv
Table Captions vi
Figure Captions vii
Chapter 1. Introduction 1
1.1 Background 1
1.2 Organization 3
Chapter 2. Related Work 4
2.1 Median Filter Architecture with Accumulative Parallel Counters 4
2.2 Modular VLSI Design of Low-cost High-efficiency Median Filter 6
Chapter 3. Proposed Architecture 8
3.1 Overview of Proposed Architecture 8
3.1.1 First NCPMU 9
3.1.2 Inter NCPMU 11
3.1.3 Last NCPMU 12
3.2 Optimization Methods 14
3.2.1 Replacing Accumulators with Counters 14
3.2.2 Adding a Constant to avoid Comparators 15
3.2.3 Adding C value to Accumulator to avoid Comparator 16
3.2.4 Removing a Comparator that detects PM = 0 18
3.2.5 Replacing XOR with AND-NOT 19
3.3 Hardware Architecture of Proposed Median Filter 20
3.3.1 First NCPMU 20
3.3.2 Inter NCPMU 21
3.3.3 Last NCPMU 22
3.3.4 Overall Structure of Proposed Median Filter 23
3.3.5 Methods used in different NCPMUs 24
Chapter 4. Experiments and Comparisons 26
4.1 Performance Comparison of Different NCPMUs 26
4.2 NCPMU Combinations 28
4.3 Comparison with Bit-Level Median Filters 31
Chapter 5. Conclusion 34
References 35

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