電漿製程，在現今的半導體產業中，是最廣為人知且用途最廣泛的一項技術。其優點在於製作微小元件之能力、控制其離子之方向性等。然而，隨著元件的進一步微縮，電漿技術的缺點也逐漸顯露，如電荷聚集影響蝕刻物輪廓、電荷轉移劣化元件電性以及極紫外光照射改變元件電性等。為了克服上述等問題，新一代的半導體製程技術即被開發:中性束系統。中性束系統是一種電漿製程的延伸，其技術的關鍵在於將帶電離子在與基板發生反應前將其中性化的技術，主要目的即用來避免在電漿製程中因為電荷聚集累積、紫外光照射所造成元件在物理輪廓及電性上的缺陷。
本論文旨在探討中性束系統應用於蝕刻製程，透過製作高介電系數氧化層/金屬閘極電容，驗證其改善傳統電漿製程缺陷的能力。本論文分為兩部分實驗，第一部份的實驗是細部探討傳統電漿系統在製程時產生的紫外光和極紫外光對於元件在電性上的影響，以及中性束系統的架構是否具改善極紫外光傷害的能力。在此實驗中，首先，作者採用了放射光譜儀分別對感應式耦合電漿及中性束系統產生的放射光做直接量測，衡量兩者在製程中產生的放射光強度，做為評估極紫外光大小的依據。其次，為了能直觀明瞭的探討紫外光在元件中造成的傷害，作者使用事先做好的電容，將其分別放置在中性束以及感應式耦合電漿系統中，照射電漿放射的極紫外光，以了解其對電容電性造成的影響。為了使實驗數據準確，在第一部分所採用的電容是透過掀離製程來定義其電容面積，元件製作過程中刻意避免電漿製程，以免額外的電漿傷害影響實驗數據的可信度。結果顯示，在感應式耦合電漿系統中量測到放射光強度是遠大於中性束系統的，證明其極紫外光照射量大於中性束。在元件電性的部分，放置在感應式耦合電漿系統中的電容，其電性的表現皆劣於放置在中性束系統中之電容。由以上結果可得知: 一、在電漿製程產生的極紫外光確實會對元件造成傷害，二、中性束系統的架構確實是具有減少極紫外光傷害的功能。
最後，為了符合業界的興趣，作者將受到照射之電容送去做氮氣加氫氣退火，以觀察退火對於受到紫外光傷害之電容的修復程度。
本論文的第二部分實驗則為分別使用中性束蝕刻系統及感應式耦合電漿蝕刻系統製作以矽鍺合金為半導體基板之電容，並對兩者在不同蝕刻機制下製作的電容做電性的分析，最後比較其平帶電壓偏移、氧化層電荷密度、介面缺陷密度及閘極漏電流等電性差異。結果顯示，由感應式耦合電漿蝕刻系統所製作之電容在電性表現上劣於中性束蝕刻所製，證明了中性束系統具有能力改善在製程中所造成的電漿傷害。

Plasma fabrication, which is one of the most well-known and utilized technology in the present semiconductor industry. The advantages of this technology are capability of fabricating minute device and ability of control the direction of the ions. However, as the dimension of the device shrinks, disadvantages of this technology start revealed and show their importance, such as charge build up effecting etched profile, charging damage degrading electrical characteristics and ultra violet (UV)/vacuum ultra violet (VUV) photons irradiation effecting electrical performance. In order to conquer the problems, a new semiconductor fabrication technology has been developed, neutral beam system. Neutral beam system is an extended application of plasma fabrication, the key of this technique is to neutralize the ions before reacting with substrate. The main purpose is to avoid plasma damages caused by charge accumulation and UV/VUV irradiation effecting both physical profile and electrical performance of the device.
In this thesis, the purport is to discuss the neutral beam system applied in etching process. Through fabricating high-k/metal gate capacitor, we would like to verify the ability of improving conventional plasma fabrication defect. In this work, the experiment is divided into two parts. The first part is focusing on the effect of ultra violet generated by traditional plasma to the device electrical characteristics, and verifying whether the neutral beam system is capable of improving the UV/VUV damage or not. First of all, the author used the optical emission spectroscopy (OES) directly to measure the emission photons generated by ICP and NBE respectively; the purpose is to evaluate the intensity of photons on the basis of UV/VUV magnitude. Second, in order to understand the damage to the device caused by UV/VUV and the diversification of electrical characteristics firsthand, the author set the pre-fabricated capacitor in the ICP and NBE system to absorb the irradiation of UV/VUV respectively. For making the information accurately, the MOS capacitor used in the first part was fabricated by lift off process; any plasma process was avoided during fabrication lest effect the reliability of the experiment data. The result shows that the photon intensity measured in ICP is far stronger than in NBE, which proves that the irradiation dosage of UV/VUV in ICP is larger than in NBE. In the device electrical performance part, the characteristics of capacitor placed in ICP system show further degradation compared to the other placed in NBE. Base on the above result, in a nutshell: (a) The UV/VUV generated by plasma fabrication does indeed effect the device performance. (b) The neutral beam system does possess the potential to reduce the damage of UV/VUV photons. Finally, in order to agree with the interest of industry, the author made the capacitor through annealing process in the atmosphere of forming gas which is N2+H2, and observe the recovery of the damaged device.
The second part of the experiment is fabricating silicon germanium based metal-oxide-semiconductor (MOS) by neutral beam etching (NBE) and inductively coupled plasma etching (ICP) respectively; the electrical performance of the capacitors under different etching mechanism are analyzed, and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current are also compared. The results show the characteristics of MOS capacitor fabricated by ICP are inferior to those made by NBE, which proves the neutral beam system is capable of improving the damages induced by conventional plasma system.

摘要 2
Abstract 4
Content 6
List of Figures 8
List of Tables 11
Chapter 1 Introduction 12
1-1 Background 12
1-1-1 Scaling of the CMOS 12
1-1-2 Application of high-k material in gate stack. 14
1-1-3 Introduction of SiGe alloy for channel material. 15
1-2 Plasma etching 15
1-2-1 Fundamental principle of plasma 15
1-2-2 Introduction of plasma etching 19
1-2-3 Principle of inductively coupled plasma (ICP) 22
1-3 Issues of conventional plasma etching technology 25
1-3-1 Charging damage 25
1-3-2 Electron shading effect 26
1-3-3 Aspect ratio dependent etching (ARDE) 28
1-3-4 Ultra violet/vacuum ultra violet irradiation damage 29
1-4 Motivation and organization of this thesis 31
Reference 32
Chapter 2 Principle of equipment and devices 36
2-1 The neutral beam etching technique 36
2-2 Optical emission spectroscopy 39
2-3 Metal-oxide-semiconductor capacitor 41
Reference 46
Chapter 3 Study of UV/VUV irradiation damaging MOS capacitor characteristics in neutral beam/inductively coupled plasma etching 48
3-1 Introduction 48
3-2 Experimental details 49
3-2-1 Neutral beam etching and inductively coupled plasma setup 49
3-2-2 Installation of optical emission spectroscopy for photon intensity measurement 51
3-2-3 Lift-off process for MOS capacitor fabrication 52
3-2-4 Exposure of MOS capacitor to UV/VUV photons irradiation 53
3-3 Result and discussion 53
3-3-1 Photon intensity measured in ICP and NBE. 53
3-3-2 Electrical characteristics analysis and comparison 56
3-3-3 Damage recovery through post-metal annealing (PMA) 66
3-4 Summary 68
Reference 69
Chapter 4 Electrical characteristics and etching performance comparison of SiGe MOS capacitor fabricated by neutral beam etching/ICP-like etching 71
4-1 Introduction 71
4-2 Experimental details 72
4-2-1 Fabrication process of SiGe MOS capacitor 72
4-2-2 Neutral beam system and configuration setup 73
4-2-3 Electrical performance and physical structure measurements 75
4-3 Results and discussion 75
4-3-1 Top view and overall capacitance (Cox) 76
4-3-2 Flat-band voltage (VFB) 77
4-3-3 Flat-band voltage shift (∆VFB) and oxide trapped charge (Qot) 79
4-3-4 Interface state density (Dit) 80
4-3-5 Leakage current density 84
4-4 Summary 85
Reference 86
Chapter 5 Conclusion 89

Ch1
[1]G. Moore, Progress in digital integrated electronics [Technical literature, Copyright 1975 IEEE. Reprinted, with permission. Technical Digest. International Electron Devices Meeting, IEEE, 1975, pp. 11-13.], IEEE Solid-State Circuits Society Newsletter, vol. 11, no. 3, pp. 36-37, 2006.
[2]R. Dennard, F. Gaensslen, H. Yu, V. Leo Rideovt, E. Bassous and A. Leblanc, Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions, IEEE Solid-State Circuits Newsletter, vol. 12, no. 1, pp. 38-50, 2007.
[3]Y. Taur and T. Ning, Fundamentals of modern VLSI devices. New York: Cambridge University Press, 2009.
[4]G. Ribes et al., Review on high-k dielectrics reliability issues, in IEEE Transactions on Device and Materials Reliability, vol. 5, no. 1, pp. 5-19, March 2005.
[5]S. H. Lo, D. A. Buchanan, Y. Taur and W. Wang, Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's, in IEEE Electron Device Letters, vol. 18, no. 5, pp. 209-211, May 1997.
[6] D. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang, and K. P. Macwilliams, “Modulation-doped p-channel Ge,Si, -, MOSFET, in DRC Conf. Dig., 1990, VIA-1.
[7] S. S. Iyer, P. M. Solomon, V. P. Kesan, J. L. Freeouf, A. A. Bright, and T. N. Nguyen, “Si/SiCe metal oxide semiconductor devices, in DRC Conf. Dig., 1990, VIA-2.
[8]P. Garone, V. Venkataraman and J. Sturni, Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures, IEEE Electron Device Letters, vol. 12, no. 5, pp. 230-232, 1991.
[9]N. Tallaj and M. Buyle-Bodin, Work function measurements on germanium by thermionic emission, Surface Science, vol. 69, no. 2, pp. 428-436, 1977.
[10]R. Minamisawa, D. Buca, B. Holländer, J. Hartmann, K. Bourdelle and S. Mantl, p-Type Ion Implantation in Tensile Si∕Compressive Si0.5Ge0.5∕Tensile Strained Si Heterostructures, Journal of The Electrochemical Society, vol. 159, no. 1, p. H44, 2012.
[11]W.R. Grove, LXXIX. On the electro-chemical polarity of gases, The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science, vol. 4, no. 28, pp. 498-514, 1852.
[12]F. Simeon, in A Discussion on “The Making of Reflecting Surfaces (The Fleetway, Imperial College of Science and Technology, South Kensington, S.W.7, 1920), pp. 26.
[13]M. Lieberman and A. Lichtenberg, Principles of plasma discharges and materials processing. Hoboken (N.J.): Interscience, 2006.
[14]V. Donnelly and A. Kornblit, Plasma etching: Yesterday, today, and tomorrow, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 31, no. 5, p. 050825, 2013.
[15]I. Hussla, K. Enke, H. Grunwald, G. Lorenz and H. Stoll, In situ silicon-wafer temperature measurements during RF argon-ion plasma etching via fluoroptic thermometry, Journal of Physics D: Applied Physics, vol. 20, no. 7, pp. 889-896, 1987.
[16]J. Coburn and H. Winters, Ion‐ and electron‐assisted gas‐surface chemistry—An important effect in plasma etching, Journal of Applied Physics, vol. 50, no. 5, pp. 3189-3196, 1979.
[17]J. Hopwood, Review of inductively coupled plasmas for plasma processing, Plasma Sources Science and Technology, vol. 1, no. 2, pp. 109-116, 1992.
[18]Kyung Seok Min, Chang Yong Kang, Ook Sang Yoo, Byoung Jae Park, Sung Woo Kim, C. Young, D. Heh, G. Bersuker, Byoung Hun Lee and Geun Young Yeom, Plasma induced damage of aggressively scaled gate dielectric (EOT ≪ 1.0nm) in metal gate/high-k dielectric CMOSFETs, 2008 IEEE International Reliability Physics Symposium, 2008.
[19]A. Martin, Review on the reliability characterization of plasma-induced damage, Journal of Vacuum Science ＆ Technology B: Microelectronics and Nanometer Structures, vol. 27, no. 1, p. 426, 2009.
[20]T. Nozawa, T. Kinoshita, T. Nishizuka, A. Narai, T. Inoue and A. Nakaue, The Electron Charging Effects of Plasma on Notch Profile Defects, Japanese Journal of Applied Physics, vol. 34, no. 1, 4, pp. 2107-2113, 1995.
[21]N. Fujiwara, T. Maruyama and M. Yoneda, Pulsed Plasma Processing for Reduction of Profile Distortion Induced by Charge Buildup in Electron Cyclotron Resonance Plasma, Japanese Journal of Applied Physics, vol. 35, no. 1, 4, pp. 2450-2455, 1996.
[22]S. Samukawa, Feature profile evolution in plasma processing using on-wafer monitoring system.
[23]H. Ohtake, S. Fukuda, B. Jinnai, T. Tatsumi and S. Samukawa, Prediction of Abnormal Etching Profile in High-Aspect-Ratio Via/Hole Etching Using On-Wafer Monitoring System, Japanese Journal of Applied Physics, vol. 49, no. 4, pp. 04DB14, 2010.
[24]Y. Liaw, W. Liao, M. Wang, C. Lin, B. Zhou, H. Gu, D. Li and X. Zou, A high aspect ratio silicon-fin FinFET fabricated upon SOI wafer, Solid-State Electronics, vol. 126, pp. 46-50, 2016.
[25]B. Wu, A. Kumar and S. Pamarthy, High aspect ratio silicon etch: A review, Journal of Applied Physics, vol. 108, no. 5, p. 051101, 2010.
[26]S. Lai, D. Johnson and R. Westerman, Aspect ratio dependent etching lag reduction in deep silicon etch processes, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 24, no. 4, pp. 1283-1288, 2006.
[27]P. Lenahan and P. Dressendorfer, Hole traps and trivalent silicon centers in metal/oxide/silicon devices, Journal of Applied Physics, vol. 55, no. 10, pp. 3495-3499, 1984.
[28]K. Yokogawa, Y. Yajima, T. Mizutani, S. Nishimatsu and K. Suzuki, Positive Charges and E' Centers Formed by Vacuum Ultraviolet Radiation in SiO2Grown on Si, Japanese Journal of Applied Physics, vol. 29, no. 1, 10, pp. 2265-2268, 1990.
[29]S. Samukawa, K. Sakamoto, and K. Ichiki, Generating high-efficiency neutral beams by using negative ions in an inductively coupled plasma source, Journal of Vacuum Science ＆ Technology A, vol. 20, pp. 1566-1573, 2002.
Ch2
[1]D. Lee, S. Jung, S. Park and G. Yeom, Characteristics of neutral beam generated by reflection on a planar-type reflector and its etching properties, Surface and Coatings Technology, vol. 177-178, pp. 420-425, 2004.
[2]S. Nam, D. Economou and V. Donnelly, Generation of Fast Neutral Beams by Ion Neutralization in High-Aspect-Ratio Holes: A Particle-in-Cell Simulation Study, IEEE Transactions on Plasma Science, vol. 35, no. 5, pp. 1370-1378, 2007.
[3]S. Abolmasov, T. Ozaki and S. Samukawa, Characterization of neutral beam source based on pulsed inductively coupled discharge: Time evolution of ion fluxes entering neutralizer, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 25, no. 1, pp. 134-140, 2007.
[4]S. Samukawa, K. Sakamoto and K. Ichiki, High-Efficiency Neutral-Beam Generation by Combination of Inductively Coupled Plasma and Parallel Plate DC Bias, Japanese Journal of Applied Physics, vol. 40, no. 2, 7, pp. L779-L782, 2001.
[5]T. Kubota, O. Nukaga, S. Ueki, M. Sugiyama, Y. Inamoto, H. Ohtake and S. Samukawa, 200-mm-diameter neutral beam source based on inductively coupled plasma etcher and silicon etching, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 28, no. 5, pp. 1169-1174, 2010.
[6]K. Miwa, Y. Nishimori, S. Ueki, M. Sugiyama, T. Kubota and S. Samukawa, Low-damage silicon etching using a neutral beam, Journal of Vacuum Science ＆ Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 31, no. 5, p. 051207, 2013.
[7]T. Mizutani and S. Nishimatsu, Sputtering yield and radiation damage by neutral beam bombardment, Journal of Vacuum Science ＆ Technology A, vol. 6, pp. 1417-1420, 1988.
[8]D. Lee, B. Park, and G. Yeom, Effects of axial magnetic field on neutral beam etching by low-angle forward-reflected neutral beam method, Japanese journal of applied physics, vol. 44, p. L63, 2004.
[9]D. Economou, Pulsed plasma etching for semiconductor manufacturing, Journal of Physics D: Applied Physics, vol. 47, no. 30, p. 303001, 2014.
[10]S. Samukawa and T. Mieno, Pulse-time modulated plasma discharge for highly selective, highly anisotropic and charge-free etching, Plasma Sources Science and Technology, vol. 5, no. 2, pp. 132-138, 1996.
[11]S. Samukawa, K. Sakamoto, and K. Ichiki, Generating high-efficiency neutral beams by using negative ions in an inductively coupled plasma source, Journal of Vacuum Science ＆ Technology A, vol. 20, pp. 1566-1573, 2002.
[12]S. Sze and K. Ng, Physics of semiconductor devices. New Dehli: Wiley-India, 2007.
Ch3
[1]S. Samukawa, K. Sakamoto and K. Ichiki, Generating high-efficiency neutral beams by using negative ions in an inductively coupled plasma source, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 20, no. 5, pp. 1566-1573, 2002.
[2]S. Samukawa, Damage-Free Plasma Etching Processes for Future Nanoscale Devices, 2009 IEEE 22nd International Conference on Micro Electro Mechanical Systems, 2009.
[3]T. Kubota, O. Nukaga, S. Ueki, M. Sugiyama, Y. Inamoto, H. Ohtake and S. Samukawa, 200-mm-diameter neutral beam source based on inductively coupled plasma etcher and silicon etching, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 28, no. 5, pp. 1169-1174, 2010.
[4]S. Samukawa, K. Sakamoto and K. Ichiki, High-Efficiency Low Energy Neutral Beam Generation Using Negative Ions in Pulsed Plasma, Japanese Journal of Applied Physics, vol. 40, no. 2, 10, pp. L997-L999, 2001.
[5]S. Samukawa, K. Sakamoto and K. Ichiki, High-Efficiency Neutral-Beam Generation by Combination of Inductively Coupled Plasma and Parallel Plate DC Bias, Japanese Journal of Applied Physics, vol. 40, no. 2, 7, pp. L779-L782, 2001.
[6]T. Yunogami, T. Mizutani, K. Suzuki and S. Nishimatsu, Radiation Damage in SiO2/Si Induced by VUV Photons, Japanese Journal of Applied Physics, vol. 28, no. 1, 10, pp. 2172-2176, 1989.
[7]J. Schwank, M. Shaneyfelt, D. Fleetwood, J. Felix, P. Dodd, P. Paillet and V. Ferlet-Cavrois, Radiation Effects in MOS Oxides, IEEE Transactions on Nuclear Science, vol. 55, no. 4, pp. 1833-1853, 2008.
[8]K. Yokogawa, Y. Yajima, T. Mizutani, S. Nishimatsu and K. Suzuki, Positive Charges andE' Centers Formed by Vacuum Ultraviolet Radiation in SiO2Grown on Si, Japanese Journal of Applied Physics, vol. 29, no. 1, 10, pp. 2265-2268, 1990.
[9]T. Tatsumi, S. Fukuda and S. Kadomura, Radiation Damage of SiO2 Surface Induced by Vacuum Ultraviolet Photons of High-Density Plasma, Japanese Journal of Applied Physics, vol. 33, no. 1, 4, pp. 2175-2178, 1994.
[10]T. Yunogami, T. Mizutani, K. Tsujimoto and K. Suzuki, Mechanism of Radiation Damage in SiO2/Si Induced by vuv Photons, Japanese Journal of Applied Physics, vol. 29, no. 1, 10, pp. 2269-2272, 1990.
[11]T. Oldham, F. McLean, H. Boesch and J. McGarrity, An overview of radiation-induced interface traps in MOS structures, Semiconductor Science and Technology, vol. 4, no. 12, pp. 986-999, 1989.
[12]K. Yokogawa, Y. Yajima, T. Mizutani, S. Nishimatsu and K. Suzuki, Positive Charges and E' Centers Formed by Vacuum Ultraviolet Radiation in SiO2Grown on Si, Japanese Journal of Applied Physics, vol. 29, no. 1, 10, pp. 2265-2268, 1990.
[13]M. Schmidt, M. Lemme, H. Kurz, T. Witters, T. Schram, K. Cherkaoui, A. Negara and P. Hurley, Impact of H2/N2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks, Microelectronic Engineering, vol. 80, pp. 70-73, 2005.
[14]D. Han, J. Kang, C. Lin and R. Han, Reliability characteristics of high-K gate dielectrics HfO2 in metal-oxide semiconductor capacitors, Microelectronic Engineering, vol. 66, no. 1-4, pp. 643-647, 2003.
[15]M. Jeng, H. Lin and J. Hwu, Rapid thermal post-metallization annealing effect on thin gate oxides, Applied Surface Science, vol. 92, pp. 208-211, 1996.
[16]L. Do Thanh, Elimination and Generation of Si-SiO[sub 2] Interface Traps by Low Temperature Hydrogen Annealing, Journal of The Electrochemical Society, vol. 135, no. 7, p. 1797, 1988.
Ch4
[1]K. Eriguchi and K. Ono, Impacts of plasma process-induced damage on MOSFET parameter variability and reliability, Microelectronics Reliability, vol. 55, no. 9-10, pp. 1464-1470, 2015.
[2]E. Koji and O. Kouichi, Quantitative and comparative characterizations of plasma process-induced damage in advanced metal-oxide-semiconductor devices, Journal of Physics D: Applied Physics, vol. 41, p. 024002, 2008.
[3]A. Martin, Review on the reliability characterization of plasma-induced damage, Journal of Vacuum Science ＆ Technology B, vol. 27, pp. 426-434, 2009.
[4]Y. Norikuni, O. Masaharu, M. Osamu, and Y. Shizuka, Surface Damage on Si Substrates Caused by Reactive Sputter Etching, Japanese Journal of Applied Physics, vol. 20, p. 893, 1981.
[5]G. Oehrlein, Dry etching damage of silicon: A review, Materials Science and Engineering: B, vol. 4, no. 1-4, pp. 441-450, 1989.
[6]B. O'Sullivan, L. Pantisano, P. Roussel, R. Degraeve, G. Groeseneken, S. DeGendt and M. Heyns, On the Recovery of Simulated Plasma Process Induced Damage in High-k Dielectrics, 2006 IEEE International Reliability Physics Symposium Proceedings, 2006.
[7]C. Young, G. Bersuker, F. Zhu, K. Matthews, R. Choi, S. Song, H. Park, J. Lee and B. Lee, Comparison of Plasma-Induced Damage in SIO2/TIN and HFO2/TIN Gate Stacks, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual, 2007.
[8]G. Bersuker, J. Barnett, N. Moumen, B. Foran, C. Young, P. Lysaght, J. Peterson, B. Lee, P. Zeitzoff and H. Huff, Interfacial Layer-Induced Mobility Degradation in High-kTransistors, Japanese Journal of Applied Physics, vol. 43, no. 11, pp. 7899-7902, 2004.
[9]S. Sze and J. Irvin, Resistivity, mobility and impurity levels in GaAs, Ge, and Si at 300°K, Solid-State Electronics, vol. 11, no. 6, pp. 599-602, 1968.
[10]S. Samukawa, K. Sakamoto and K. Ichiki, Generating high-efficiency neutral beams by using negative ions in an inductively coupled plasma source, Journal of Vacuum Science ＆ Technology A: Vacuum, Surfaces, and Films, vol. 20, no. 5, pp. 1566-1573, 2002.
[11]P. Rai-Choudhury, J. Benton, D. Schroder and T. Shaffner, Diagnostic Techniques for Semiconductor Materials and Devices. Bellingham: SPIE, 1997.
[12]E. Nicollian and J. Brews, MOS (metal oxide semiconductor) physics and technology. New York: Wiley, 1982.
[13]A. Goetzberger, E. Klausmann and M. Schulz, Interface states on semiconductor/insulator surfaces, C R C Critical Reviews in Solid State Sciences, vol. 6, no. 1, pp. 1-43, 1976.
[14]G. DeClerck, Characterization of Surface States at the Si-SiO2 Interface, Nondestructive Evaluation of Semiconductor Materials and Devices, pp. 105-148, 1979.
[15]E. Nicollian and A. Goetzberger, The Si-SiO2Interface - Electrical Properties as Determined by the Metal-Insulator-Silicon Conductance Technique, Bell System Technical Journal, vol. 46, no. 6, pp. 1055-1133, 1967.
[16]D. Schroder, Semiconductor material and device characterization. [Piscataway, NJ]: IEEE Press, 2006.
[17]R. Fowler and L. Nordheim, Electron Emission in Intense Electric Fields, Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences, vol. 119, no. 781, pp. 173-181, 1928.
[18]M. Lenzlinger and E. Snow, Fowler‐Nordheim Tunneling into Thermally Grown SiO2, Journal of Applied Physics, vol. 40, no. 1, pp. 278-283, 1969.
[19]Z. Weinberg, On tunneling in metal‐oxide‐silicon structures, Journal of Applied Physics, vol. 53, no. 7, pp. 5052-5056, 1982.