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研究生:孔致遠
研究生(外文):Chih-YuanKung
論文名稱:一個基於時序適應性窗口之每秒取樣十萬次的十位元低功耗逐漸趨近式類比數位轉換器
論文名稱(外文):A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window
指導教授:張順志
指導教授(外文):Soon-Jyh Chang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:英文
論文頁數:114
中文關鍵詞:逐漸趨近式類比數位轉換器時域窗口適應性窗口低功耗低電壓
外文關鍵詞:SAR ADCtiming windowadaptive windowlow-powerlow-voltage
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本論文提出一個使用適應性窗口每秒取樣十萬次的十位元低功耗逐漸趨近式類比數位轉換器。本研究運用記錄比較器的運作時間,創造出適應性窗口運作機制,與過去的窗口技巧相比,適應性窗口可以更積極地減少DAC、比較器以及數位電路的耗能,另外使用時域來創造窗口可以避免比較器發生亞穩態而導致後級電路不正常運作的情況發生。
本設計以台積電90奈米CMOS標準1P9M製程實作晶片,核心電路面積佔140 μm × 420 μm。量測結果顯示,在0.35伏特電源供電及每秒取樣十萬次的操作速度下,訊號雜訊比之最大值為57.18分貝,換算之有效位元數9.21位元,消耗功率為74 nW,每次資料所消耗的能量為1.25 fJ。
This thesis presents a 0.35 V 100 kS/s 10-bit successive approximation register (SAR) ADC with adaptive window (AW) in 90 nm CMOS. The SAR ADC uses the transient information of the latch comparator to create redundancy ranges. Furthermore, the proposed technique also uses the transient information to produce AW for each bit which reduces the power consumption of the comparator, the DAC and also digital control logic. Last but not least, the timing control window can also decrease the possibility ADC from encountering meta-stability. The measurement result achieves an SNDR of 57.18 dB, an ENOB of 9.2 bits, a power consumption of 74 nW, and a resulting FoM of 1.25 fJ/conv.-step.
Chapter 1 Introduction 1
1.1 BACKGROUND AND MOTIVATION 1
1.2 ORGANIZATION 4
Chapter 2 Fundamentals of Analog-to-Digital Converters 6
2.1 THE BASICS OF ANALOG TO DIGITAL CONVERTER 6
2.1.1 Quantization Error 7
2.1.2 Resolution 10
2.1.3 Accuracy 10
2.2 STATIC SPECIFICATIONS 11
2.2.1 Offset Error 12
2.2.2 Gain Error 13
2.2.3 Nonlinearity 14
2.3 DYNAMIC SPECIFICATIONS 16
2.3.1 Signal-to-Noise Ratio 17
2.3.2 Signal-to-Noise and Distortion Ratio 18
2.3.3 Effective Number of Bits 18
2.3.4 Spurious Free Dynamic Range 18
2.3.5 Total Harmonic Distortion 19
2.3.6 Effective Resolution Bandwidth (ERBW) 20
2.3.7 Figure of Merit (FoM) 21
2.4 TYPES OF NYQUIST RATE ADCS 21
2.4.1 Flash ADC 22
2.4.2 Pipelined ADC 23
2.4.3 Successive-Approximation Register ADC 26
Chapter 3 Introduction of SAR ADCs 28
3.1 BASICS OF SAR ADCS 28
3.1.1 The Concepts of SAR ADC Operation 29
3.1.2 Circuit Operation of the SAR Architecture 31
3.2 CAPACITOR SWITCHING METHODS OF SAR ADCS 33
3.2.1 Conventional Capacitor Switching Procedure 36
3.2.2 Monotonic Capacitor Switching Method 37
3.2.3 Split-monotonic Capacitor Switching Method 39
3.3 ERROR TOLERANCE OF SAR ADCS 40
3.3.1 Redundant Error Compensation of SAR ADCs 41
3.3.2 Window Error Tolerance Functions 45
3.3.3 Tolerable Errors 53
Chapter 4 A Low Power SAR ADC with Time-based Adaptive Window 63
4.1 INTRODUCTION 63
4.2 ARCHITECTURAL CONSIDERATION 65
4.2.1 The Timing Window Structure 66
4.2.2 Circuit Operation Procedure 67
4.3 PROPOSED ADAPTIVE WINDOW TECHNIQUE 68
4.3.1 Comparator Transient Response 68
4.3.2 Adaptive Window Scheme 70
4.3.3 Comparison with Other Window Techniques 74
4.4 ARCHITECTURE OF PROPOSED SAR ADC 75
4.5 CIRCUIT IMPLEMENTATION 78
4.5.1 Double Bootstrapped Switch 78
4.5.2 Dynamic Two-Stage Comparator 80
4.5.3 Delay Cells and Imitation Delay Circuit 81
4.5.4 Digital Control Logic Circuits 83
4.5.5 Capacitor DAC Array 88
Chapter 5 Simulation and Measurement Results 91
5.1 LAYOUT AND CHIP FLOOR PLAN 91
5.2 SIMULATION RESULTS 94
5.3 DIE MICROGRAPH AND MEASUREMENT SETUP 97
5.4 MEASUREMENT RESULTS 99
Chapter 6 Conclusions and Future Works 105
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