臺灣博碩士論文加值系統

The transistor size was well scaled by following Moore’s law for sub-20 nm and beyond with the introduction of FinFETs, which were the revolutionary upgrades for the manufacturers until they (FinFETs) started experiencing various issues at sub-10 nm and beyond. It was then the concept of Gate-All-Around (GAA) nanowire took over the attention of the semiconductor industry for sub-7 nm node and beyond. But soon the designers started facing the complex scaling issues and lithography limitations with FinFETs and GAA nanowires at sub-5 nm node and beyond. Moreover, effective width of GAA nanowires were also small which limited the drive currents. It was not later in mid of 2017, the researchers at IBM announced a breakthrough of successful fabrication of nanosheet FETs at sub-5 nm node and that it can solve the issues faced by FinFETs and nanowires enabling scaling even beyond sub-5 nm. Also, if proper EUV lithography is made available then nanosheets may aid in less complex patterning aiming suitable for sub-5 nm node completely replacing FinFETs.

In this thesis we show the how the electrical performance of nanosheet FETs can be enhanced. This is a simulation study using Synopsis Sentaurus TCAD. We simulated the dopingless Si-nanosheet FET with Metal Insulator Semiconductor (MIS) contacts at source and drain (SD). The simulation results are compared with doped Si-nanosheet FET with Metal Semiconductor (MS) contacts. It is shown that former has more prominent immunity to short-channel effects i.e., better subthreshold swing (SS), reduced threshold voltage roll-off, suppressed DIBL. Being undoped it has better immunity to problems caused by traditional doping (like random dopant fluctuation, thermal budget and mobility degradation), also using MIS contacts aids in Fermi level de-pinning and reduced parasitic resistance and induce free carriers at the SD thereby, increasing overall device performance.

Abstract I
誌謝 II
Contents III
Table captions V
Figure captions VI
Chapter Ⅰ Introduction 1
1-1 Moore's law and its Importance 1
1-2 Device Scaling 2
1-2-1 Ground Scaling law for multi-gate and stacked devices 3
1-3 Short Channel Effect 6
1-4 IBM Breakthrough 7
1-5 FinFET reaching scaling limits 7
1-6 Effective Width (Weff) 8
1-7 Intrinsic Performance 10
1-8 Inner Spacer option 13
1-9 Motivation 14
1-10 Organization of Thesis 14
Chapter Ⅱ Introduction to TCAD and S Device Models 15
2-1 Sentaurus TCAD 15
2-2 Features of Synopsys Sentaurus TCAD 16
2-2-1 Sentaurus Workbench (SWB) 16
2-2-2 Sentaurus Device Editor 16
2-2-3 S Device 17
2-2-4 Inspect 18
2-2-5 Sentaurus Visual 18
2-3 S Device Models used in Simulations 18
2-3-1 Fermi Statistics 19
2-3-2 Mobility Models 19
2-3-3 Band-to-Band Tunneling (BTBT) 20
2-3-4 Bandgap Narrowing Models 20
2-3-5 Non-local Meshing ＆ Non-local Tunneling 21
2-3-6 Recombination Models 22
2-3-7 S Device Physics section 23
Chapter III Dopingless Si NSH-FET with MIS contacts 25
3-1 Issues related to traditional chemical doping 25
3-1-1 Random Dopant Fluctuation (RDF) 25
3-1-2 Thermal Budget (TB) 26
3-1-3 Mobility Degradation 26
3-2 Dopingless Devices 27
3-3 MS and MIS contacts 28
3-3-1 Issues related to Metal Semiconductor (MS) contacts 28
3-4 Previous work using MIS contacts 30
3-5 Dopingless Si NSH-FET with MIS contacts 37
3-6 Summary 38
Chapter IV Simulation Results and Discussion 39
4-1 Structure details simulated in SDE 39
4-1-1 Traditionally doped Si NSH-FET with MS-SD contacts 39
4-1-2 Sentaurus Device Editor 41
4-2 SDevice details 42
4-3 Results and Discussion 43
4-3-1 Transfer characteristics due to different Tb 44
4-3-2 Transfer characteristics due to different W 45
4-3-3 Transfer characteristics due to different Lch 46
4-3-4 Short-channel Effect (SCE) 47
Chapter V Conclusion and Future works 51
5-1 Conclusion 51
5-2 Future works 51
References 53
Appendix I SDE Command Lines 58
Appendix II SDevice Command Lines 62
Appendix III Parameter file used in simulations 65

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[1]K.-H. Kao and L.-Y. Chen, “A dopingless FET with metal–insulator–semiconductor contacts, IEEE Electron Device Lett., vol. 38, no. 1, pp. 5–8, Jan. 2017, doi: 10.1109/LED.2016.2628414.
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Chapter V references

[1]S. M. Y. Sherazi, J. K. Chae, P. Debacker, L. Matti, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, A. Dounde, and J. Ryckaert CFET standard-cell design down to 3Track height for node 3nm and below, Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096206 (20 March 2019); https://doi.org/10.1117/12.2514571