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研究生:胡芷瑄
研究生(外文):Hu, Chih Hsuan
論文名稱:利用電漿增強型原子沉積法沉積氮化鋁/氧化鋁介電層來改善二硫化鉬場效電晶體之研究
論文名稱(外文):The Study of Using AlN/Al2O3 Dielectric with Plasma Enhanced Atomic Layer Deposition to Improve MoS2 MOSFET Performance
指導教授:張 翼,馬哲申
指導教授(外文):Chang, Edward-YiMaa, Jer Shen
口試委員:孫台平張立侯拓宏曾院介
口試委員(外文):Sun, Tai-PingChang, LiHou, Tuo-HungTseng, Yuan-Chieh
口試日期:2018-4-30
學位類別:碩士
校院名稱:國立交通大學
系所名稱:光電系統研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:英文
論文頁數:67
中文關鍵詞:二硫化鉬電晶體電漿增強型原子沉積介電層沉積
外文關鍵詞:MoS2 FETPEALDdielectric deposition
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依照摩爾定律進行CMOS微縮帶來了許多好處,但大量的漏電流愈來愈多受到重視。 在這種情況下,MoS2的超薄體(UTB)半導體可以充分增加柵極對通道的控制並減少漏電流。然而,在二維材料上均勻生長小於10nm厚度的介電質仍然具有很大的挑戰性。 在這項研究中,成功地使用了電漿增強行原子沉積ALD (PEALD),在低溫(150℃)條件下製作了具有1nm AlN和6nm Al2O3介電質的閘極 MoS2 FET。元件具有很高的開/關電流比106,場效遷移率為9.5cm2/Vs,次臨界擺幅(SS)為 171mV/dec,這些結果與類似結構的元件相比,具有相當不錯的電性表現。此外,我們通過TLM測量來分別得到有與沒有介電質覆蓋的接觸電阻,並且比較介電質的覆蓋對背閘極 MOS2 FET的影響。
The pace of the CMOS scaling following Moore’s law brings many benefits, but large off-state leakage has become a growing concern. In this regime, the ultra-thin-body (UTB) semiconductor of MoS2 can sufficiently increase gate-to-channel control and reduce current leakage. While the uniform growth of sub-10nm dielectrics on 2D materials still remains challenging. In this work, we successfully use plasma enhanced ALD (PEALD) to demonstrate a high performance top-gated MoS2 FET with 1nm AlN and 6nm Al2O3 top-gate dielectric at low temperature (150℃). The device exhibits high on/off current ratio about 106, the field-effect mobility of 9.5cm2/Vs, and the subthreshold swing (SS) of 171 mV/dec, which is comparable to the similar structure of the top gate device. In addition, we do TLM measurement to extract our contact resistance with and without the dielectric capping and compare the effect of the dielectric capping on the back-gate MOS2 FETs.
摘要 i
Abstract ii
誌謝 iii
Content iv
Table Caption vi
Figure Caption vii
Chapter 1 1
Introduction 1
1.1 General Back Ground 1
1.2 Motivation 3
1.3 Thesis Outline 4
Chapter 2 7
Literature Review 7
2.1 Overview of Molybdenum Disulfide (MoS2) Basis 7
2.1.1 Crystal Structure of MoS2 7
2.2 Exfoliated Method of MoS2 8
2.2.1 Mechanical Exfoliation of MoS2 9
2.2.2 Liquid-Phase Ultrasonication Exfoliation of MoS2 9
2.2.3 Lithium-Based Chemical Exfoliation of MoS2 10
2.3 Methods to Achieved Uniform Growth of High-κ Materials on MoS2 by ALD 10
2.3.1 Surface Functionalization 10
2.3.2 Inserting a Buffer Layer 13
2.3.3 Plasma-Enhanced ALD (PEALD) Process 15
Chapter 3 30
Fabrication Process and Measurement 30
3.1 Standard Fabrication Process of Exfoliated MoS2 FETs 30
3.1.1 Mark Substrate Fabrication 31
3.1.2 Mechanical Exfoliated of MoS2 32
3.1.3 Mesa Isolation 32
3.1.4 Ohmic Metal Deposition 33
3.1.5 Dielectric Deposition 34
3.1.6 Gate Metal Deposition 35
3.1.7 Dielectric Via 35
3.2 Fabrication Process of MoS2 MOS Capacitor 36
3.3 Material and Characteristic Measurement 36
3.3.1 Material Characteristic Measurements 36
3.3.2 Leakage Measurement for Gate Oxide 37
3.3.3 CV Measurement for Gate Oxide 37
3.3.4 DC Measurement 37
3.3.5 Transmission Line Measurement (TLM Measurement) 38
Chapter 4 46
Result and Discussion 46
4.1 Overview 46
4.2 The Improvement of Dielectric Deposition on MoS2 46
4.2.1 Leakage Measurement 46
4.2.2 CV Measurement 48
4.3 Device Performance of Top-Gated MoS2 MOSFET with 1nm AlN and 6nm Al2O3 48
4.3.1 DC Measurement 48
4.4 The Effect of Back-gated MoS2 MOSFET with and without Dielectric Capping 50
4.4.1 Transmission Line Measurement (TLM Measurement) 50
Chapter 5 57
Conclusion 57
References 59
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