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研究生(外文):Wang, Ying-Chieh
論文名稱(外文):Study of π-gate InAs HEMT for Logic Application
指導教授(外文):Chang, Edward-Yi
口試委員(外文):Chang, LiXie, Zong-YongWu, Janne-Wha
外文關鍵詞:InAsHEMTLogic Application
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結果顯示π型閘極電晶體比平面電晶體在低偏壓下(VDS=0.5V)具有更好的邏輯特性,元件展現了較低的次臨界擺62.7mV/decade、斷態電流0.00935mA/mm與較大的開關電流比3.5 x 104。由這些研究結果可以證實,π型閘極砷化銦通道高電子遷移率電晶體極有潛力作為未來後矽半導體世代高速邏輯電晶體的使用。
Recently, the planar transistors with sub-micro-scale gates have already been the trend of semiconductor industry. Many researches still focus on reducing gate length. However, as the transistor scales down, many problems start appearing, such as VTH roll-off and off-state leakage, or so called short channel effect. Therefore, searching a new channel material and a corresponding fabrication process are urgent to improve the device characteristics.
InAs channel with high electron mobility and low threshold voltage. It matches with InP substrate as well. As a result, we use InAlAs/InAs/InP high electron mobility transistors (HEMTs) to achieve high-speed and low power consumption in this study. Furthermore, by double electron beam lithography and etching, we let the foot of the π-gate directly connect to the bottom InAlAs-buffer layers. Because the gate was connected to both the upper InAlAs and bottom InAlAs-buffer layers and form Shottky contact , the potential energy of the both InAlAs layers was shifted to positive direction when the gate voltage increases. This resulted in the InXGa1-XAs/InAs/InXGa1-XAs layer potential shifts to the positive direction, resulting in the higher electron concentration at the channel. This is the reason for low subthreshold swing (SS) and high ION/IOFF ratio for the π-gate InAs HEMTs.
The results showed that the 3-D π-gate devices present better logic parameter, including lower SS of 62.7 mV/decade, lower off-state leakage current of 0.00935mA/mm and larger ION/IOFF ratio of 3.5 x 104 for low power logic applications(VDS=0.5V).
摘要 I
Abstract III
誌 謝 V
Figure Captions VIII
Table Captions XI
Chapter 1 1
Introduction 1
1.1 Background 1
1.2 Motivations 2
1.3 Thesis Organization 3
Chapter 2 7
Overview of III-V 3-D devices for Logic Applications 7
2.1 The theory of III-V Devices 7
2.2 The InAs/InP HEMTs in this work 8
2.3 HEMTs’ Figures of Merit for Logic Applications 8
2.4 Evaluations of III-V HEMTs for Beyond-CMOS Logic Applications 11
2.5 Evaluations of 3-D π-gate HEMTs for Conventional HEMTs 12
Chapter 3 18
Experimental Design and Fabrication Process 18
3.1 Mesa Isolation 19
3.2 Ohmic Contact formation 19
3.3 Definition of Hole Etching Region by E-beam Lithography and Etching Process 20
3.4 Device Passivation 20
3.5 Definition of Gate Recess Region by Electron Beam Lithography and Etching Process 21
3.6 Gate Formation and Gate Metal Deposition 22
3.7 Nitride Via Dry Etch 22
3.8 Electron Microscope Images of 3-D Devices 22
Chapter 4 29
Fundamentals of Electronic Characteristics 29
4.1 DC Characteristics [30] 29
4.2 Transmission Line Model (TLM) 32
4.3 Scattering Parameters [33] 32
4.5 Current-Gain Cutoff Frequency (fT) and Maximum Oscillation Frequency (fmax) 34
4.6 Device Modeling Technology 35
Chapter 5 42
Experimental Results and Discussions 42
5.1 Device Measurement 42
5.2 DC Characteristics Comparison between π-gate and planar devices. 42
Chapter 6 53
Conclusions 53
Reference 63
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