隨著製程越來越先進，電子元件的尺寸持續微縮，基於製程上的限制與可製造性上的考量，設計規範也越趨複雜。標準元件是組成數位電路的基本元件，因此電路的效能有極大部分取決於標準元件的品質，所以在複雜的設計規範之下，產生高品質的標準元件成為了一個重要的課題。複雜的設計規範的特點在於設計規範會隨著目標物件與其周遭物件的關聯性而有所不同，並且擁有數種不同的可能數值。本篇論文將先針對先進製程中常出現的複雜設計規範加以介紹，並且為了解決複雜的設計規範在設計標準元件佈局圖所帶來的困難與挑戰，對於已完成繞線但不通過設計規範驗證的標準元件作後繞線處理。並且，在解決修正佈局圖中違反複雜設計規範的區域的同時，我們將藉由加入多餘的contact以提升佈局圖流通的電流量並進而提升標準元件的效能。實驗結果證實，經過我們的優化之後，912顆無法通過設計規範驗證的標準元件中有98%可以通過設計規範驗證，並且在效能方面也有明顯的提升。

With the progress of technology node, the design rules become more complex because of manufacturing limitation coming from tiny feature size. Standard cells are the basic elements and widely used in digital IC designs. Standard cells impact the qualities of IC designs substantially. The challenges of complex design rules contain multiple rules and/or multiple values related to a victim object and its surrounding objects. This paper proposes a post-routing optimization framework applying to routed cell layouts without considering several common complex design rules during routing. Furthermore, this framework also improves cell performance through adding redundant contacts to increase the current flowing through a cell. We apply the proposed framework on 912 cells and 98% cells can obtain violation-free result along with significantly improved cell quality.

摘要 I
ABSTRACT II
Acknowledgement III
Contents IV
List of Figures V
Chapter 1. Introduction 1
Chapter 2. Preliminary 3
2.1 Layout Structure 3
2.2 Complex Design Rules and Related Design Challenges 5
2.3 Problem Formulation 10
Chapter 3. Methodology 11
3.1 Solve Contact Space Violation 12
3.2 Add Contact and Via Enclosure 15
3.3 Enclosure and Metal Area 18
3.4 Wire Plow 20
3.5 Redundant Contact Insertion 22
3.6 Line-end 24
3.7 Expand Metal Area 26
3.8 Roll-back Operation 28
Chapter 4. Experimental Result 29
Chapter 5. Conclusions 33
References 34

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