(3.238.36.32) 您好!臺灣時間:2021/02/27 08:40
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳敬禾
研究生(外文):Chen, Ching-Ho
論文名稱:考慮先進製程複雜的設計規則之標準元件庫佈局圖最佳化
論文名稱(外文):Standard Cell Layout Optimization Considering Complex Design Rules for Advanced Technology Nodes
指導教授:李毅郎
指導教授(外文):Li, Yih-Lang
口試委員:吳凱強李育民
口試委員(外文):Wu, Kai-ChiangLee, Yu-Min
口試日期:2017-10-25
學位類別:碩士
校院名稱:國立交通大學
系所名稱:資訊科學與工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:英文
論文頁數:34
中文關鍵詞:標準元件設計規則先進製程
外文關鍵詞:Standard CellDesign RuleAdvanced Technology Nodes
相關次數:
  • 被引用被引用:0
  • 點閱點閱:93
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程越來越先進,電子元件的尺寸持續微縮,基於製程上的限制與可製造性上的考量,設計規範也越趨複雜。標準元件是組成數位電路的基本元件,因此電路的效能有極大部分取決於標準元件的品質,所以在複雜的設計規範之下,產生高品質的標準元件成為了一個重要的課題。複雜的設計規範的特點在於設計規範會隨著目標物件與其周遭物件的關聯性而有所不同,並且擁有數種不同的可能數值。本篇論文將先針對先進製程中常出現的複雜設計規範加以介紹,並且為了解決複雜的設計規範在設計標準元件佈局圖所帶來的困難與挑戰,對於已完成繞線但不通過設計規範驗證的標準元件作後繞線處理。並且,在解決修正佈局圖中違反複雜設計規範的區域的同時,我們將藉由加入多餘的contact以提升佈局圖流通的電流量並進而提升標準元件的效能。實驗結果證實,經過我們的優化之後,912顆無法通過設計規範驗證的標準元件中有98%可以通過設計規範驗證,並且在效能方面也有明顯的提升。
With the progress of technology node, the design rules become more complex because of manufacturing limitation coming from tiny feature size. Standard cells are the basic elements and widely used in digital IC designs. Standard cells impact the qualities of IC designs substantially. The challenges of complex design rules contain multiple rules and/or multiple values related to a victim object and its surrounding objects. This paper proposes a post-routing optimization framework applying to routed cell layouts without considering several common complex design rules during routing. Furthermore, this framework also improves cell performance through adding redundant contacts to increase the current flowing through a cell. We apply the proposed framework on 912 cells and 98% cells can obtain violation-free result along with significantly improved cell quality.
摘要 I
ABSTRACT II
Acknowledgement III
Contents IV
List of Figures V
Chapter 1. Introduction 1
Chapter 2. Preliminary 3
2.1 Layout Structure 3
2.2 Complex Design Rules and Related Design Challenges 5
2.3 Problem Formulation 10
Chapter 3. Methodology 11
3.1 Solve Contact Space Violation 12
3.2 Add Contact and Via Enclosure 15
3.3 Enclosure and Metal Area 18
3.4 Wire Plow 20
3.5 Redundant Contact Insertion 22
3.6 Line-end 24
3.7 Expand Metal Area 26
3.8 Roll-back Operation 28
Chapter 4. Experimental Result 29
Chapter 5. Conclusions 33
References 34
[1] T. Jhaveri et al, "Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings," in IEEE Trans. CAD, vol. 29, Issue 4, pp. 509-527, 2010.
[2] R. R. Schaller, "Moore's law: past, present and future," in IEEE Spectrum, vol. 34, Issue 6, pp.52-59, 1997.
[3] Takao Uehara and William M. Vancleemput, "Optimal Layout of CMOS Functional Arrays," in IEEE Trans. CAD, vol. C-30, Issue 5, pp. 305-312, 1981.
[4] C. J. Poirier, “Excellerator: Custom CMOS Leaf Cell Layout Generator,” in IEEE Trans. CAD, vol. 8, Issue 7, pp. 744-755, 1989.
[5] Y.-C. Hsieh et al, “LiB: A Cell Layout Generator,” in Proc. of the 48th ACM/IEEE DAC, 1990.
[6] Mohan Guruswamy et al, "CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries," in Proc. of the 34th DAC, pp. 327-332, 1997.
[7] Jaewon Kim and S. M. Kang, “An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design,” in Proc. of the 34th DAC, pp. 456-459, 1997.
[8] A. Gupta and J.P. Hayes, “Optimal 2-D Cell Layout with Integrated Transistor Folding,” in Proc. of ACM/IEEE ICCAD, pp. 128-138, 1998.
[9] N. Ryzhenko and S. Burns, "Physical Synthesis onto a Layout Fabric with Regular Diffusion and Polysilicon Geometries," in Proc. of the 48th ACM/IEEE DAC, pp. 83-88, 2011.
[10] N. Ryzhenko and S. Burns, “Standard Cell Routing via Boolean Satisfiability,” in Proc. of the 48th ACM/IEEE DAC, pp. 603-612, 2012.
[11] Stefan Hougardy et al, "BonnCell: Automatic Layout of Leaf Cells," in Proc. of the 18th ASP-DAC, pp. 453-460, 2013.
[12] J. Cortadella et al, "A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing," in IEEE Trans. CAD, vol. 33, Issue 3, pp. 409-422, 2014.
[13] Hsueh-Ju Lu et al, “Practical ILP-Based Routing of Standard Cells,” in Proc. of IEEE DATE, pp. 245-548, 2016.
[14] Pascal Cremer et al, “Automatic Cell Layout in the 7nm Era,” in ACM ISPD, pp. 99-106, 2017.
[15] M. Cote and P. Hurat, “Standard Cell Printability Grading and Hot Spot Detection,” in ISQED, pp. 264-269, 2005.
[16] M. Cote and P. Hurat, “Layout Printability Optimization using a Silicon Simulation Methodology,” in SCS, pp. 159-164, 2004.
[17] Nikolai Ryzhenko and Steven Burns, "Physical Synthesis onto a Layout Fabric with Regular Diffusion and Polysilicon Geometries," in Proc. of the 48th ACM/IEEE DAC, pp. 83-88, 2011.
[18] Kaushik Vaidyanathan et al, "Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic," in ACM/IEEE ICCAD, pp. 124-131, 2014.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
無相關期刊
 
無相關點閱論文
 
系統版面圖檔 系統版面圖檔