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研究生:許峻齊
研究生(外文):Hsu , Chun-Chi
論文名稱:電阻式記憶體循環操作後導致讀取干擾錯誤時間劣化之研究
論文名稱(外文):SET/RESET Cycling Induced Read-Disturb Failure Time Degradation in a Resistive Switching Memory
指導教授:汪大暉
指導教授(外文):Wang, Tahui
口試委員:陳一浸盧道政謝光宇
口試日期:2017
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:英文
論文頁數:45
中文關鍵詞:電阻式記憶體讀取干擾錯誤時間
外文關鍵詞:Resistive Switching MemoryRead Disturb Failure Time Degradation
相關次數:
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  • 下載下載:5
  • 收藏至我的研究室書目清單書目收藏:0
在本篇論文中,吾人探討電阻式記憶體在高密度的陣列中,元件於低組值態下的讀取干擾錯誤時間,和在多次的寫入/抹除操作之後,讀取錯誤干擾時間逐漸縮短劣化的現象。吾人推測這是由於在寫入/抹除的操作過程中,電阻式記憶體的介電層會逐漸產生一些不同於氧空缺的缺陷,這些缺陷和氧空缺在電流傳導中均扮演角色,共同組成低組值態的電流導通路徑,導致元件在相同阻值的低組值態下,氧空缺的總數量下降。由於寫入/抹除操作產生的新缺陷不能與氧原子結合而湮滅,因此在施加讀取干擾電壓作用時,氧離子進入電阻式記憶體的介電質中僅能與氧空缺結合並還原,代表著只能氧化傳導路徑上部分關鍵位置,因此造成電流傳導路徑更容易斷開,致使讀取干擾錯誤時間大幅縮短。此外,本篇論文透過實驗發現於正偏壓、小電壓的讀取干擾情況下,氧空缺湮滅的速率會遵循冪定律的形式,吾人據此建立一個定量解析模型,成功描述讀取干擾錯誤時間縮短的原因與其劣化的程度,並能透過實驗結合模型萃取出此種缺陷的產生速率。這些探討有助於了解元件劣化背後的物理原因以及判斷讀取偏壓的設計是否合理,對於電阻式記憶體的發展有相當的貢獻。
In this thesis, SET/RESET cycling stress induced low-resistance state (LRS) read disturb failure time degradation in the tungsten oxide resistive switching memory is investigated. A strong power law time-dependence (~t^n) of oxygen vacancy annihilation is experimentally discovered, where the power factor n is range from -0.1 to -0.2 and has a voltage dependence. This thesis exposes that the read disturb immunity in a LRS cell gradually degrades several orders of magnitude with cycle number increases before the RESET endurance failure. Simultaneously, a progressive increase of low-field current dominating by trap-assisted tunneling in the rupture region is noticed. To gain a further understanding into this phenomenon, constant voltage stress method is applied to simulate the stress effect during SET/RESET cycling and evaluate the trap generation mechanism in the switching dielectric. These stress-induced oxides traps replace for some of the oxygen vacancies and participate in forming conductive percolation paths, leading to a diminished density of oxygen vacancy and thus causing the degradation of LRS read disturb failure time. For the first time, the stress-induced oxide traps generation rate in a tungsten oxide RRAM is extracted, and an analytical model based on the concept of oxide trap creation is proposed to explain the correlation between stress-induced oxide traps and LRS read disturb failure time degradation. The proposed model in this thesis can well emulate the progressive degradation behavior both in constant voltage stress and cycling stress, confirming that the degradation of read disturb immunity can be attributed to stress-induced oxide traps.
Chinese Abstract i
English Abstract iii
Acknowledgement v
Contents vii
Figure Captions viii
Chapter 1 Introduction 1
Chapter 2 Characterization of Stress-Induced LRS Read Disturb Failure time degradation 7
2.1 Introduction 7
2.2 Device structure and measurement setup 7
2.3 LRS Read Disturb Failure Mechanism Discussion 9
2.4 Stress-Induced LRS Read Disturb Failure Time Degradation 12
Chapter 3 Read Disturb Failure Time Degradation
Model 30
3.1 Introduction 30
3.2 Analytical Modeling of Constant Voltage Stress Induced Read Disturb Failure Time Degradation 30
3.3 Analytical Modeling of Constant Voltage Stress Induced Read Disturb Failure Time Degradation 30
Cycling Induced Read Disturb Failure Time Degradation Model 32
Chapter 4 Conclusion 39
References 40
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