臺灣博碩士論文加值系統

本論文針對穿隧式場效電晶體與鰭式場效電晶體於類比低壓降線性穩壓器與數位線性穩壓器應用作探討與分析。我們利用Sentaurus三維TCAD混合模式模擬器針對電晶體的物理特性進行模擬與分析，並且利用HSPICE電路模擬軟體配合經TCAD模擬器校準過的查表式Verilog-A進一步針對電路進行模擬。

針對類比低壓降線性穩壓器(LDO)，由於穿隧式場效電晶體的傳輸機制不同於傳統電晶體，因此我們從電晶體的角度出發探討其轉移電導、輸出阻抗與本質增益的特性，可以發現在低壓下，穿隧式場效電晶體可以提供較好的表現；然而鰭式場效電晶體在電流驅動能力上佔有優勢，因而可以將之應用於高效能類比電路。進一步，我們利用上述兩電晶體針對鰭式線性穩壓器、穿隧式線性穩壓器和混合式線性穩壓器就頻率響應、暫態響應與電源抑制比(PSRR)著手討論。研究結果分析指出，在超低耗功率應用下，由於穿隧式電晶體具有較好的本質增益與飽和特性，因此在相同操作電流設計下，穿隧式線性穩壓器與混合式線性穩壓器可提供較鰭式線性穩壓器的迴路增益與電源抑制比。

隨著操作電壓的下降，類比線性穩壓器的表現會劇烈衰退，因此在低操作電壓下，數位線性穩壓器進而成為理想的選擇。在0.5伏特的操作電壓下，首先我們針對其中的數位誤差偵測器(DED)進行分析，模擬結果指出，鰭式誤差偵測器的偵測速率可較穿隧式誤差偵測器快上約莫70倍以上。再者，以鰭式誤差偵測器作為偵測源，我們針對後續的充放電幫浦端就鰭式幫浦、混合式幫浦與平行式幫浦三種架構做討論，研究分析顯示，由於穿隧式場效電晶體於0.5伏特的操作電壓下電流驅動能力遠不及於鰭式場效電晶體，因此將鰭式場效電晶體應用於數位線性穩壓器的表現是最具優勢的。

This thesis focuses on analog low-dropout linear voltage regulator and digitally controlled linear voltage regulator with FinFET, TFET and Hybrid TFET-FinFET implementations. We use Sentaurus atomistic 3D TCAD mixed-mode to analysis fundamental physical characteristics of transistors. Also, Verilog-A look-up table calibrated with simulation results from TCAD is applied in HSPICE circuit simulation tool for further analysis.

In exploration of analog low-dropout linear voltage regulator (LDO), because the transport mechanism of TFET is different from conventional MOSFET and FinFET, we do investigation of transconductance, output resistance and intrinsic gain of devices at first. It can be observed that, TFET demonstrates better performance at low operating voltage, while FinFET exhibits outperformance in current drive ability which is an advantage in high-performance applications. Furthermore, the performance of FinFET-LDO, TFET-LDO and Hybrid-LDO including frequency response, transient response and power supply rejection ration (PSRR) are evaluated. The results indicate that for ultra-low power application, TFET-LDO and Hybrid-LDO provide better loop-gain and PSRR than FinFET-LDO under comparable operating current design.

As operating voltage further reduced, the performance of analog LDO degrades severely; therefore, digitally controlled linear voltage regulator becomes the choice. Firstly, we analyze the digital error detector (DED) based on FinFET and TFET at 0.5V operating voltage. The sense period of TFET-DED is 7x times longer than FinFET-DED. Next step, we investigate the performance of pull/push devices under FinFET, Hybrid and Parallel structures based on FinFET-DED. The results demonstrate FinFET applied in digitally controlled voltage regulator stands out at 0.5V operating voltage due to the relatively strong current drive ability.

摘要 I
Abstract II
誌謝 III
Contents IV
Table Caption VI
Figure Caption VII
Chapter 1 1
Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 3
Chapter 2 6
Device Analysis of TFET and FinFET 6
2.1 Introduction 6
2.2 Device Design 7
2.2.1 Characteristic of TFET Device 7
2.2.2 Device Structures and Parameters 9
2.3 Simulation Methodogies 11
2.4 Summary 12
Chapter 3 19
Analog Low-Dropout Linear Voltage Regulator 19
3.1 Introduction 19
3.2 Devices Characteristic and Analog Parameters 21
3.2.1 Delayed saturation of TFET 21
3.2.2 Analog Parameters 22
3.3 Circuit Simulation 24
3.3.1 LDO Structure and Operation 24
3.3.2 Frequency Response 25
3.3.3 Transient Response 28
3.3.4 Power Supply Rejection Ratio (PSRR) 29
3.3.5 Performance as Supply Voltage Scaling 30
3.4 Summary 31
Chapter 4 43
Digital Linear Voltage Regulator 43
4.1 Introduction 43
4.2 Circuit Simulation 44
4.2.1 Digital Voltage Regulator Structure 44
4.2.2 Digital Error Detector (DED) 46
4.2.3 Simulation Result 47
4.3 Summary 50
Chapter 5 60
Conclusions 60
Reference 64

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