本篇論文利用源極/汲極側壁微縮通道長度，搭配氮化矽側壁硬式光罩蝕刻法形成奈米通道，可以I-line微影技術成功製備等效通道長度小於100奈米，面積微縮至約16x30〖奈米〗^2的全環繞式閘極多晶矽奈米線電晶體，並以無摻雜以及高摻雜濃度多晶矽通道，分別實現反轉式與無接面式電晶體。另外，本篇論文運用原子層化學氣相沉積(ALD)二氧化鉿以及氮化鈦形成高介電係數金屬閘極(HK/MG)結構，利用ALD的高包覆力與均勻性，成功將HK/MG整合於前述環繞式閘極奈米線電晶體結構中。實驗結果說明小尺寸HK/MG元件之次臨界擺幅(SS)最低能達到70 (mV/dec)，平均值也能達到90 (mV/dec)左右，而小尺寸多晶矽閘極(PG)元件之平均SS亦落在100 (mV/dec)左右，展現出環繞式閘極結構的高閘極控制力。
我們於實驗結果發現通道越長，SS表現越差之趨勢，此與通道中段的陷落有關。而透過比較與分析每種元件結構之SS和V_th，我們發現HK/MG元件的SS在對EOT做正規化後，會比PG表現差。另外，兩種元件長通道反轉式電晶體V_th的差異會大於兩種閘極材料功函數的差異，這樣的現象源自於PG元件中帶正電的介面固定電荷以及HK/MG元件中的介面固定電荷。最後，我們分析比較不同元件之閘極引起之汲極漏電流(GIDL)的特性，發現其與閘極和汲極跨壓(V_gd)呈高相關性，且此關聯性只跟閘極層結構相關，與通道材料無太大關係，比較後發現，HK/MG元件GIDL電流為〖10〗^(-11) A時的V_gd=V_(gd,th)約為-0.75V，而PG元件的V_(gd,th)約為-3.2V，且HK/MG的GIDL電流與V_gd呈現較強烈的相關性，這個現象是因為HK/MG元件有較小的EOT與較嚴重的缺陷所導致。

In this thesis, making use of I-line lithography in conjunction with S/D sidewall-spacers to shorten the channel length and 〖Si〗_3 N_4 sidewall-spacer hard mask (HM) etching method to form the nanowire channel, we are able to fabricate gate-all-around (GAA) polysilicon (poly-Si) nanowire(NW) FET with effective gate length (L_eff) less than 100nm and the area of the NW channel around 16x30〖nm〗^2. Solid-phase crystallization (SPC) poly-Si and in-situ n^+ doped poly-Si are employed as the channel for inversion mode (IM) and junctionless (JL) mode devices, respectively. Furthermore, we successfully implement the high-k/metal gate (HK/MG) structure into the GAA NWFET thanks to the high conformity of ALD processes. Short-channel HK/MG devices exhibit SS as low as 70 (mV/dec), and the mean SS is about 90 (mV/dec). Short-channel poly-Si-gated (PG) devices show the SS of around 100 mV/dec. The good SS performance of the devices confirms the excellent gate controllability of the GAA structure regardless of the type of the gate stack. Improved SS in the HK/MG devices is attributed to the lower EOT. However, we find that SS tends to increase with increasing channel length. The degradation of SS performance in the long-channel devices is owing to the falling of the central NW to the substrate as it is suspended.
By comparing the electrical characteristics of all devices, we find that the mean SS of HK/MG devices after the normalization is not better than that of PG devices which can be attributed to the fact that there are more interface defects contained in HK/MG split. And the anomalously high V_th is observed in HK/MG devices, it can be attributed to the positive interface fixed charges in PG devices and the negative interface fixed charges in HK/MG devices.
We also study the gate induced drain leakage (GIDL)-like current in all splits, and identify its high dependence on gate-to-drain voltage (V_gd). We find that the relation between GIDL-like current and V_gd is mainly related to the type of gate stack. The V_(gd,th) of HK/MG devices is about -0.75, and the V_(gd,th) of PG devices is about -3.2V where V_(gd,th) is defined as the V_gd at I_d=〖10〗^(-11) A. Moreover, the GIDL-like current shows stronger dependence to V_gdfor HK/MG devices than PG ones. The above phenomenon can be attributed to the smaller EOT and higher density of defects in the HK/MG devices.

摘要 ……………………………………………………… i
Abstract ……………………………………………………… ii-iii
Acknowledgement ……………………………………………………… iv
Contents ……………………………………………………… v
Table Captions ……………………………………………………… vi
Figure Captions ……………………………………………………… vii-xii
Chapter 1 Introduction ………………………………………… 1-10
1.1 Background……………………………………………………………………………………… 1-2
1.1.1 Overview of High-k/Metal Gate (HK/MG) ……………… 2-6
1.1.2 Overview of Multiple-Gate Structures ………………… 6-7
1.1.3 Junctionless (JL) Nanowire Field Effect Transistor (NWFET)……… 7-9
1.2 Motivation…………………………………………………………………………………………………………………… 9-10
1.3 Organization of the Thesis …………………………………… 10
Chapter 2 Devices Fabrication and Measurement Setup ……… 11-17
2.1 Process Flow and Device Structure ………………………… 11-15
2.2 Extractions of Electrical Parameters ………………………… 15-17
2.2.1 Sub-threshold Swing (SS) …………………………………… 15
2.2.2 Threshold Voltage (V_th) ………………………………… 15-17
Chapter 3 Results and Discussion ……………………………………… 18-30
3.1 Reduction of Effective Gate Length by S/D Sidewall-Spacer Method …… 18-19
3.2 Cross-Sectional Profile of the Nanowire Channel ………… 19-20
3.3 Basic Electrical Characteristics ……………………………… 20-30
3.3.1 Subthreshold Swing ………………………………………… 21-24
3.3.2 Threshold Voltage …………………………………………… 24-26
3.3.3 Gate Induced Drain Leakage (GIDL)-Like Current ……………… 26-28
Chapter 4 Conclusion and Future Work ……………………………………… 29-31
4.1 Conclusions ……………………………………………………… 29-30
4.2 Future Work ……………………………………………………… 30-31
Tables and Figures ………………………………………………………………… 32-89
Reference ………………………………………………………………… 90-93

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