(3.238.7.202) 您好!臺灣時間:2021/03/01 22:00
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:李曉菁
研究生(外文):Li, Siao-Jing
論文名稱:高介電係數金屬閘極全環繞式多晶矽奈米線電晶體製備與特性研究
論文名稱(外文):Fabrication and Characterization of High-k/Metal Gate Gate-All-Around Polysilicon Nanowire FET
指導教授:林鴻志林鴻志引用關係
指導教授(外文):Lin, Horng-Chih
口試委員:林鴻志張睿達趙天生李佩雯
口試委員(外文):Lin, Horng-ChihChang, Ruey-DarChao, Tien-ShengLi, Pei-Wen
口試日期:2017-09-15
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:英文
論文頁數:94
中文關鍵詞:高介電係數材料金屬閘極無接面電晶體奈米線全環繞式電晶體閘極引起之汲極漏電流
外文關鍵詞:High-kMetal gateJunctionless FETNanowireGate-all-around FETGIDL
相關次數:
  • 被引用被引用:0
  • 點閱點閱:82
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文利用源極/汲極側壁微縮通道長度,搭配氮化矽側壁硬式光罩蝕刻法形成奈米通道,可以I-line微影技術成功製備等效通道長度小於100奈米,面積微縮至約16x30〖奈米〗^2的全環繞式閘極多晶矽奈米線電晶體,並以無摻雜以及高摻雜濃度多晶矽通道,分別實現反轉式與無接面式電晶體。另外,本篇論文運用原子層化學氣相沉積(ALD)二氧化鉿以及氮化鈦形成高介電係數金屬閘極(HK/MG)結構,利用ALD的高包覆力與均勻性,成功將HK/MG整合於前述環繞式閘極奈米線電晶體結構中。實驗結果說明小尺寸HK/MG元件之次臨界擺幅(SS)最低能達到70 (mV/dec),平均值也能達到90 (mV/dec)左右,而小尺寸多晶矽閘極(PG)元件之平均SS亦落在100 (mV/dec)左右,展現出環繞式閘極結構的高閘極控制力。
我們於實驗結果發現通道越長,SS表現越差之趨勢,此與通道中段的陷落有關。而透過比較與分析每種元件結構之SS和V_th,我們發現HK/MG元件的SS在對EOT做正規化後,會比PG表現差。另外,兩種元件長通道反轉式電晶體V_th的差異會大於兩種閘極材料功函數的差異,這樣的現象源自於PG元件中帶正電的介面固定電荷以及HK/MG元件中的介面固定電荷。最後,我們分析比較不同元件之閘極引起之汲極漏電流(GIDL)的特性,發現其與閘極和汲極跨壓(V_gd)呈高相關性,且此關聯性只跟閘極層結構相關,與通道材料無太大關係,比較後發現,HK/MG元件GIDL電流為〖10〗^(-11) A時的V_gd=V_(gd,th)約為-0.75V,而PG元件的V_(gd,th)約為-3.2V,且HK/MG的GIDL電流與V_gd呈現較強烈的相關性,這個現象是因為HK/MG元件有較小的EOT與較嚴重的缺陷所導致。
In this thesis, making use of I-line lithography in conjunction with S/D sidewall-spacers to shorten the channel length and 〖Si〗_3 N_4 sidewall-spacer hard mask (HM) etching method to form the nanowire channel, we are able to fabricate gate-all-around (GAA) polysilicon (poly-Si) nanowire(NW) FET with effective gate length (L_eff) less than 100nm and the area of the NW channel around 16x30〖nm〗^2. Solid-phase crystallization (SPC) poly-Si and in-situ n^+ doped poly-Si are employed as the channel for inversion mode (IM) and junctionless (JL) mode devices, respectively. Furthermore, we successfully implement the high-k/metal gate (HK/MG) structure into the GAA NWFET thanks to the high conformity of ALD processes. Short-channel HK/MG devices exhibit SS as low as 70 (mV/dec), and the mean SS is about 90 (mV/dec). Short-channel poly-Si-gated (PG) devices show the SS of around 100 mV/dec. The good SS performance of the devices confirms the excellent gate controllability of the GAA structure regardless of the type of the gate stack. Improved SS in the HK/MG devices is attributed to the lower EOT. However, we find that SS tends to increase with increasing channel length. The degradation of SS performance in the long-channel devices is owing to the falling of the central NW to the substrate as it is suspended.
By comparing the electrical characteristics of all devices, we find that the mean SS of HK/MG devices after the normalization is not better than that of PG devices which can be attributed to the fact that there are more interface defects contained in HK/MG split. And the anomalously high V_th is observed in HK/MG devices, it can be attributed to the positive interface fixed charges in PG devices and the negative interface fixed charges in HK/MG devices.
We also study the gate induced drain leakage (GIDL)-like current in all splits, and identify its high dependence on gate-to-drain voltage (V_gd). We find that the relation between GIDL-like current and V_gd is mainly related to the type of gate stack. The V_(gd,th) of HK/MG devices is about -0.75, and the V_(gd,th) of PG devices is about -3.2V where V_(gd,th) is defined as the V_gd at I_d=〖10〗^(-11) A. Moreover, the GIDL-like current shows stronger dependence to V_gdfor HK/MG devices than PG ones. The above phenomenon can be attributed to the smaller EOT and higher density of defects in the HK/MG devices.
摘要 ……………………………………………………… i
Abstract ……………………………………………………… ii-iii
Acknowledgement ……………………………………………………… iv
Contents ……………………………………………………… v
Table Captions ……………………………………………………… vi
Figure Captions ……………………………………………………… vii-xii
Chapter 1 Introduction ………………………………………… 1-10
1.1 Background……………………………………………………………………………………… 1-2
1.1.1 Overview of High-k/Metal Gate (HK/MG) ……………… 2-6
1.1.2 Overview of Multiple-Gate Structures ………………… 6-7
1.1.3 Junctionless (JL) Nanowire Field Effect Transistor (NWFET)……… 7-9
1.2 Motivation…………………………………………………………………………………………………………………… 9-10
1.3 Organization of the Thesis …………………………………… 10
Chapter 2 Devices Fabrication and Measurement Setup ……… 11-17
2.1 Process Flow and Device Structure ………………………… 11-15
2.2 Extractions of Electrical Parameters ………………………… 15-17
2.2.1 Sub-threshold Swing (SS) …………………………………… 15
2.2.2 Threshold Voltage (V_th) ………………………………… 15-17
Chapter 3 Results and Discussion ……………………………………… 18-30
3.1 Reduction of Effective Gate Length by S/D Sidewall-Spacer Method …… 18-19
3.2 Cross-Sectional Profile of the Nanowire Channel ………… 19-20
3.3 Basic Electrical Characteristics ……………………………… 20-30
3.3.1 Subthreshold Swing ………………………………………… 21-24
3.3.2 Threshold Voltage …………………………………………… 24-26
3.3.3 Gate Induced Drain Leakage (GIDL)-Like Current ……………… 26-28
Chapter 4 Conclusion and Future Work ……………………………………… 29-31
4.1 Conclusions ……………………………………………………… 29-30
4.2 Future Work ……………………………………………………… 30-31
Tables and Figures ………………………………………………………………… 32-89
Reference ………………………………………………………………… 90-93
References
[1] "Tunneling and High-K Metal Gate (HK/MG) Stack, NCTU, Hsinchu, Taiwan, p.p. 12-15.," ed.
[2] "Brattain, Walter. Bell Labs Logbook. pp. 7–8, 24., December, 1947. https://www.pbs.org/transistor/science/labpages/labpg5.html.."
[3] Y.-C. Chen, "Characterization of N-type Gate-All-Around Nanowire Inversion-Mode, Accumulation Mode, and Junctionless Poly-Silicon Thin Film Transistors Fabricated by Nitride-Spacer Hardmask Methods," Master, Electronics Engineering, National Chiao-Tung University Hsinshu, Taiwan, 2016.
[4] M. Bohr, "A 30 Year Retrospective on Dennard's MOSFET Scaling Paper," IEEE Solid-State Circuits Society Newsletter, vol. 12, no. 1, pp. 11-13, 2007.
[5] J. P. Colinge et al., "Junctionless Transistors: Physics and Properties," in Semiconductor-On-Insulator Materials for Nanoelectronics Applications, A. Nazarov, J. P. Colinge, F. Balestra, J.-P. Raskin, F. Gamiz, and V. S. Lysenko, Eds. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011, pp. 187-200.
[6] J. S. Kilby, "Invention of The Integrated Circuit," IEEE Transactions on Electron Devices, vol. 23, no. 7, pp. 648-654, 1976.
[7] G. E. Moore, "Cramming More Components Onto Integrated Circuits," Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, 1998.
[8] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LebBlanc, "Design Of Ion-Implanted MOSFET's With Very Small Physical Dimensions," IEEE Journal of Solid-State Circuits, vol. 9, no. 5, p. 13, Oct. 1974.
[9] "The Scaling of MOSFETs, Moore’s Law, and ITRS," pp. 7-46. [Online]. Available.
[10] G. Baccarani, M. R. Wordeman, and R. H. Dennard, "Generalized Scaling Theory and Its Application To A 1/4 Micrometer MOSFET Design," IEEE Transactions on Electron Devices, vol. 31, no. 4, pp. 452-462, 1984.
[11] Z. H. Liu et al., "Threshold Voltage Model For Deep-Submicrometer MOSFETs," IEEE Transactions on Electron Devices, vol. 40, no. 1, pp. 86-95, 1993.
[12] K. Mistry et al., "A 45nm Logic Technology With High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," in 2007 IEEE International Electron Devices Meeting, 2007, pp. 247-250.
[13] C. H. Jan et al., "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized For Ultra Low Power, High Performance and High Density SoC Applications," in 2012 International Electron Devices Meeting, 2012, pp. 3.1.1-3.1.4.
[14] T. Skotnicki and C. STMicroelectronics, France, "Heading For Decananometer CMOS –Is Navigation Among Icebergs Still A Viable Strategy?," presented at the Solid-State Device Research Conference, 11-13 Sept. 2000, 2000. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1503644&isnumber=32253
[15] Y.-C. Yeo, T.-J. King, and C. Hu, "Direct Tunneling Leakage Current and Scalability of Alternative Gate Dielectrics," Applied Physics Letters, vol. 81, no. 11, pp. 2091-2093, 2002.
[16] Saeed Mohsenifar and M. H. Shahrokhabadi, "Gate Stack High-κ Materials For Si-Based MOSFETs Past, Present, and Futures," Microelectronics and Solid State Electronics, p. 13, 2015/04/01 2015.
[17] J. Robertson and R. M. Wallace, "High-K Materials and Metal Gates For CMOS Applications," Materials Science and Engineering: R: Reports, vol. 88, pp. 1-41, 2015/02/01/ 2015.
[18] H.-H. T. a. Ph.D, "The Progress and Challenges of Applying High-k/Metal-Gated Devices to Advanced CMOS Technologies," in Solid State Circuits Technologies, J. W. Swart, Ed. USA: In Tech, 2010.
[19] G. C. F. Yeap, S. Krishnan, and L. Ming-Ren, "Fringing-Induced Barrier Lowering (FIBL) in Sub-100 nm MOSFETs with High-K Gate Dielectrics," Electronics Letters, vol. 34, no. 11, pp. 1150-1152, 1998.
[20] J. Esan, S. Sunhae, J. Jae Won, and K. Kyung Rok, "Gate Induced Drain Leakage Reduction With Analysis of Gate Fringing Field Effect on High-κ/Metal Gate CMOS Technology," Japanese Journal of Applied Physics, vol. 54, no. 6S1, p. 06FG10, 2015.
[21] B. Ryu and K. J. Chang, "Defects Responsible For The Fermi Level Pinning in n+ poly-Si/HfO2 gate stacks," Applied Physics Letters, vol. 97, no. 24, p. 242910, 2010.
[22] J.-P. Colinge, "Multiple-Gate SOI MOSFETs," Solid-State Electronics, vol. 48, no. 6, pp. 897-905, 2004/06/01/ 2004.
[23] I. Ferain, C. A. Colinge, and J.-P. Colinge, "Multigate Transistors As the Future of Classical Metal-Oxide-Semiconductor Field-Effect Transistors," Nature, 10.1038/nature10676 vol. 479, no. 7373, pp. 310-316, 11/17/print 2011.
[24] T. Sekigawa and Y. Hayashi, "Calculated Threshold-Voltage Characteristics of An XMOS Transistor Having An Additional Bottom Gate," Solid-State Electronics, vol. 27, no. 8, pp. 827-828, 1984/08/01/ 1984.
[25] D. Hisamoto, T. Kaga, Y. Kawamoto, and E. Takeda, "A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET," IEEE Electron Device Letters, vol. 11, no. 1, pp. 36-38, 1990.
[26] P. Jong-Tae, J. P. Colinge, and C. H. Diaz, "Pi-Gate SOI MOSFET," IEEE Electron Device Letters, vol. 22, no. 8, pp. 405-406, 2001.
[27] Y. Fu-Liang et al., "25 nm CMOS Omega FETs," in Digest. International Electron Devices Meeting, 2002, pp. 255-258.
[28] J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, "Silicon-on-Insulator 'Gate-All-Around Device'," in International Technical Digest on Electron Devices, 1990, pp. 595-598.
[29] S. Thompson et al., "Source/Drain Extension Scaling for 0.1 /spl mu/m and Below Channel Length MOSFETs," in 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216), 1998, pp. 132-133.
[30] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, "Junctionless Multigate Field-Effect Transistor," Applied Physics Letters, vol. 94, no. 5, p. 053511, 2009.
[31] J.-P. Colinge et al., "Nanowire Transistors Without Junctions," Nat Nano, 10.1038/nnano.2010.15 vol. 5, no. 3, pp. 225-229, 03//print 2010.
[32] J. P. Colinge, "Junctionless Transistors," in 2012 IEEE International Meeting for Future of Electron Devices, Kansai, 2012, pp. 1-2.
[33] J.-P. Colinge et al., "Reduced Electric Field in Junctionless Transistors," Applied Physics Letters, vol. 96, no. 7, p. 073510, 2010.
[34] H. C. Lin, C. H. Kuo, G. J. Li, C. J. Su, and T. Y. Huang, "Operation of A Novel Device With Suspended Nanowire Channels," IEEE Electron Device Letters, vol. 31, no. 5, pp. 384-386, 2010.
[35] W. C. Chen, H. H. Hsu, Y. C. Chang, H. C. Lin, and T. Y. Huang, "Investigations of Performance Enhancement in A Poly-Si Nanowire FET Featuring Independent Double-Gated Configuration and Its Nonvolatile Memory Applications," in Proceedings of 2010 International Symposium on VLSI Technology, System and Application, 2010, pp. 142-143.
[36] C. J. Su, T. I. Tsai, Y. L. Liou, Z. M. Lin, H. C. Lin, and T. S. Chao, "Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels," IEEE Electron Device Letters, vol. 32, no. 4, pp. 521-523, 2011.
[37] C. H. Kuo, H. C. Lin, I. C. Lee, H. C. Cheng, and T. Y. Huang, "A Novel Scheme For Fabricating CMOS Inverters With Poly-Si Nanowire Channels," IEEE Electron Device Letters, vol. 33, no. 6, pp. 833-835, 2012.
[38] C. C. Yang, Y. C. Chen, H. C. Lin, R. D. Chang, P. W. Li, and T. Y. Huang, "Fabrication and RTN Characteristics of Gate-All-Around Poly-Si Junctionless Nanowire Transistors," in 2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, pp. 64-65.
[39] I. L. Cheng, L. Ko-Hui, L. Horng-Chih, and H. Tiao-Yuan, "Fabrication of Tri-Gated Junctionless Poly-Si Transistors Wwith I-line Based Lithography," Japanese Journal of Applied Physics, vol. 53, no. 4S, p. 04EA01, 2014.
[40] M. Claes et al., "Effect of Postdeposition Anneal Conditions on Defect Density of HfO2 Layers Measured by Wet Etching," Journal of The Electrochemical Society, vol. 151, no. 11, pp. F269-F275, November 1, 2004 2004.
[41] K. Chyuan-Haur, L. Chao-Sung, and L. Chung-Len, "The TEOS Oxide Deposited on Phosphorus In-Situ/POCl3 Doped Polysilicon With Rapid Thermal Annealing in N2O," IEEE Transactions on Electron Devices, vol. 45, no. 9, pp. 1927-1933, 1998.
[42] S. W. Jeong et al., "Effects of Annealing Temperature on the Characteristics of ALD-Deposited HfO2 in MIM capacitors," Thin Solid Films, vol. 515, no. 2, pp. 526-530, 2006/10/25/ 2006.
[43] A. Ortiz-Conde, A. Cerdeira, M. Estrada, F. J. Garcı́a Sánchez, and R. Quintero, "A Simple Procedure to Extract the Threshold Voltage of Amorphous Thin Film MOSFETs In the Saturation Region," Solid-State Electronics, vol. 45, no. 5, pp. 663-667, 2001/05/01/ 2001.
[44] S. Vitale, J. Kedzierski, P. Healey, P. W. Wyatt, and C. L. Keast, Work-Function-Tuned TiN Metal Gate FDSOI Transistors for Subthreshold Operation. 2011, pp. 419-426.
[45] P. McIntyre, "Bulk and Interfacial Oxygen Defects in HfO2 Gate Dielectric Stacks: A Critical Assessment," ECS Transactions, vol. 11, no. 4, pp. 235-249, September 28, 2007 2007.
[46] T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, "The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling," in 1987 International Electron Devices Meeting, 1987, vol. 33, pp. 718-721.
[47] "Tunneling and High-K Metal Gate (HK/MG) Stack, NCTU, Hsinchu, Taiwan, p.p. 19-20.."
[48] I. C. Chen, C. W. Teng, D. J. Coleman, and A. Nishimura, "Interface Trap-Enhanced Gate-Induced Leakage Current in MOSFET," IEEE Electron Device Letters, vol. 10, no. 5, pp. 216-218, 1989.
[49] S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices," Nano Letters, vol. 8, no. 2, pp. 405-410, 2008/02/01 2008.
[50] M. Kobayashi and T. Hiramoto, "Device Design Guideline For Steep Slope Ferroelectric FET Using Negative Capacitance in Sub-0.2V Operation: Operation Speed, Material Requirement and Energy Efficiency," in 2015 Symposium on VLSI Technology (VLSI Technology), 2015, pp. T212-T213.
[51] M. H. Lee et al., "Prospects for Ferroelectric HfZrOX FETs with Experimentally CET=0.98nm, SSfor=42mV/dec, SSrev=28mV/dec, Switch-off <0.2V, and Hysteresis-Free Strategies," in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 22.5.1-22.5.4.
[52] M. H. Lee et al., "Physical Thickness 1.x nm Ferroelectric HfZrOx Negative Capacitance FETs," in 2016 IEEE International Electron Devices Meeting (IEDM), 2016, pp. 12.1.1-12.1.4.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔