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研究生:江岳竺
研究生(外文):Chiang, Yueh-Chu
論文名稱:整合型扇出技術實現28GHz低雜訊放大器應用在第五代行動通訊
論文名稱(外文):A 28GHz Low Noise Amplifier(LNA) using Integrated Fan-out(InFO) technology for 5th generation wireless system
指導教授:黃國威黃國威引用關係林國瑞林國瑞引用關係
指導教授(外文):Huang, Guo WeiLin, Gray
口試委員:邱佳松陳俊淇陳坤明
口試委員(外文):Chiu, Chia-SungChen, Chun-ChiChen, Kun-Ming
口試日期:2017-9-28
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:英文
論文頁數:55
中文關鍵詞:扇出技術低雜訊放大器
外文關鍵詞:fan outLNA
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在本論文中,我們利用扇出式封裝技術製造具高品質因子的被動元件去與主動元件(TSMC 28nm CMOS)整合實現出低雜訊放大器,此低雜訊放大器設計架構為L型阻抗匹配的單級放大器應用在第五代行動通訊頻譜(28GHz)上。此論文分為低雜訊放大器的設計方法以及整合扇出式封裝製程來討論。
首先我們利用先進設計系統(ads)2009U1軟體來模擬探討出CMOS與前端以及後端匹配電路的S參數關係來達到高增益和低雜訊的最佳匹配設計與製程條件的選定,匹配電路皆由曲折式電感以及指叉式電容組成,由於我們是先經由高頻雜訊量測系統量測選定的28nm電晶體再進行模擬,電晶體在28GHz的最低雜訊為2 db以及增益為8.54 db,可以得知最佳的gamma點,再將該點進行輸入端阻抗匹配點可得到最佳的增益,也因為不是經由電晶體模組進行的模擬可免除電晶體製程造成頻率以及特性的漂移。製程方面使用的扇出式技術為晶圓級封裝,其為解決未來無法延續摩爾定律的有效方法,優點為增強在射頻電路應用的特性、有較低的功率損耗與高接腳數以及有效減少新進製程面積,因為我們可以有效利用扇出式技術中的重分佈線路層(RDL)進行被動元件的製作,利用此技術與主動元件之積體電路相結合將電路佔據大面積的被動電路皆實現在三維系統中,將有助於射頻積體電路未來增進效能及降低成本。
近年來,從國內外的專利趨勢上,可以發現到扇出技術應用在半導體中有大幅的成長,顯示出其未來的國際發展潛力和重要性。
In this thesis, we integrate passive components of high-quality factor manufactured by fan-out packaging technology with active components (TSMC 28nm CMOS), together to assemble low noise amplifier(LNA). The structure of LNA is single stage amplifier of L-shaped matching network applied under the 5th generation mobile spectrum (28GHz). This thesis is divided into the design method of LNA and integrated fan-out package process.
First, we use advanced design system (ads), 2009U1 software, not only to simulate s-parameters relationship between CMOS and input&output matching networks, but also to achieve best matching design of high gain and low noise and to select the proper process conditions. In our experiment, matching circuit is composed of meander inductors and interdigitated capacitors. We first measure the selected 28 nm transistor by the high frequency noise measurement system and proceed our simulations. Thus, we can obtain gamma optimum point and make a good use of it to do input impedance matching and then get higher gain. The results showed that the minimum noise is at 2 db and gain is at 8.54 db. Because the simulation is carried out by transistor measurement data rather than module, we can skip CMOS process and avoid its shifting characteristic. The fan-out technology used in the process is wafer-level package, which is an effective way to continue Moore's Law in the future. With advantages like enhancing the application of RF circuit characteristics, a lower power loss, high pin count (I/O) and effectively reducing the advanced process area, we can effectively use the Redistribution Layer (RDL) in fan-out technology to make passive components. The usage of this technology to integrate passive components with active components in three-dimensions will improve performance and cost down.
In recent years, from domestic to foreign patents, it can be found that the applications of fan-out technology in the semiconductor has grown substantially, showing its future international development potential.
Abstract (in Chinese)................................................i
Abstract (in English)..............................................iii
Acknowledgments ……………...................................................v
Contents...............................................vi
Figure Captions......................................viii

Chapter 1:Introduction
1.1 Background……..…...…………………..………..…….….….…........……..1
1.2 Motivation…………………………….….……..……….....………………………...2
1.3 Thesis Organization…..……………….......………….…...........2

Chapter 2:Low noise amplifier basic concept and design method
2.1 LNA basic concept…………..……………………………………………………………………………6
2.1-1 Noise Source…………………………………………………………………………………………7
2.2 LNA designed method…………….………………………………………………………………….13
2.2-1 Common LNA structure…………………………………………………………………13
2.2-2 LC matching method………………………………………………………………………19
2.3 LNA layout design…………………………………………………………………………………………23
2.3-1 CPW meander inductor…………………………………………………………………24
2.3-2 CPW Interdigitated Capacitor……………………………………………24
2.3-3 LNA layout design…………………………………………………………………………25
Chapter 3:InFO technology & fabrication
3.1 Fan-out introduction…………………………………………………………………………………26
3.2 NDL manufacturing technology introduction ………………………………..……………………………………………………………………………………………………………28
3.3 InFO process flow………………….……………………………………………………………………30

Chapter 4:Measurement system introduction and discussion
4.1 High frequency noise parameter measurement system introduction…………………………………………………………………………………………………………………40
4.2 High frequency noise parameter measurement system calibration and measurement method……………………………………………………………………………………………………………………………….41
4.3 Measurement results and discussion………………………………………………………………………………………………………………………47

Chapter 5:Conclusion…………….….……………………………………………………………………51
References………………………………………………………………………………………………………………………52
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[1.3] K. Yang. (2016, Jun 7). IC封裝新技術發展趨勢. [Online]. Available: https://www.slideshare.net/KentYang2/ic-62795343
[1.4] K. Joosse, “Advanced Heterogeneous Solutions for System Integration,” TSMC., Israel., 2015.
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[1.6] http://www.patentinspiration.com/
[2.1] Behzad Razavi, RF MICROELECTRONICS, 2nd ed. Prentice Hall, 2011.
[2.2] A. Van Der Ziel, Noise in Solid-State Device and Circuits, New York: Weley, 1986.
[2.3] D.K. Shaeffer, T.H. Lee, “A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier,” IEEE J. Solid-State Circuits., vol. 32, no. 5, pp. 745-759, May 1997.
[2.4] Reinhold Ludwig, Pavel Bretchko, RF Circuit Design: Theory and Applications, vol. 1, Prentice Hall, 2000.
[2.5] Aleksandar B. Menicanin, Ljiljana D. Zivanov, Mirjana S. Damnjanovic, Andrea M. Maric, “Low-Cost CPW Meander Inductors Utilizing Ink-Jet Printing on Flexible Substrate for High-Frequency Applications,” IEEE Trans. Electron Devices., vol. 60, no. 2, pp. 827-832, Feb. 2013.
[2.6] M. Naghed, I. Wolff, “Equivalent Capacitances of Coplanar Waveguide Discontinuities and Interdigitated Capacitors Using a Three-Dimensional Finite Difference Method,” IEEE Trans. Microw. Theory Techn.,vol. 38, no. 12, pp. 1808-1815, Dec. 1990.
[3.1] Christianto C. Liu, et al., “High-Performance Integrated Fan-Out Wafer Level Packaging (InFO-WLP): Technology and System Integration,” IEEE IEDM, pp. 14.1.1-14.1.4, Dec. 2012.
[3.2] Che-Wei Hsu, et al, “High Performance Chip-Partitioned Millimeter Wave Passive Devices on Smooth and Fine Pitch InFO RDL,” in Proc. 67th Annu. IEEE Electron. Compon. Technol. Conf., June 2017, pp. 254-259.
[3.3] Chung-Hao Tsai, et al, “High Performance Passive Devices for Millimeter Wave System Integration on Integrated Fan-Out (InFO) Wafer Level Packaging Technology,” IEEE IEDM, pp. 25.2.1 - 25.2.4, Dec. 2015.
[3.4] Chuei-Tang Wang, et al, “Power Saving and Noise Reduction of28nm CMOS RF System Integration Using Integrated Fan-Out Wafer Level Packaging (InFO-WLP) Technology,” in Proc. IEEE 2015 International 3D Systems Integration Conference, Sept. 2015, pp. TS6.3.1 - TS6.3.4.
[3.5] NAIP Newsletter. (2015, Oct. 7). 散出型晶圓級構裝 (Fan-Out WLP)之技術與挑戰 [Online]. Available: http://www.naipo.com/Portals/1/web_tw/Knowledge_Center/Research_Development/publish-131.htm
[3.6] Phil Garrou. (2015, Nov. 16). IFTLE 261 Consolidation Continues; the Info on InFO?; RTI 3D ASIP [Online]. Available: http://electroiq.com/insights-from-leading-edge/2015/11/iftle-261-consolidation-continues-the-info-on-info-rti-3d-asip/
[4.1] Huan-Che Lin, “An LST Calibration Method for Broadband Measurement,” M.S. dissertation, Dept. Communication Engineering, Yuan-Ze Univ., Taoyuan, R.O.C., 2005 . .
[4.2] CascadeMicrotech. (2007). Impedance Standard Substrate [Online]. Available: https://www.cascademicrotech.com/files/iss_map_101-190.pdf
[4.3] 葉景祥. (2009, Jan. 15) Introduction S parameter calibration method [Online]. Available: http://ddl.cic.org.tw/servlets/org.cic.internal.tpd.enews.enewsdownload?D_no=442&D_id=99&filename=442.pdf&sessionid=f569b2f622fc4ec08588efd83bccfe86
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