在高介電常數金屬閘極鰭狀場效電晶體中，電偶極子於二氧化鉿/二氧化矽介面的產生與擾動是一值得重視的課題，因此現象會造成奈米及半導體元件之臨界電壓偏移並對整體元件之良率有相當的衝擊。在此篇論文中，藉由現代三維電腦科技輔助軟體模擬的輔助，我們可以單獨對電偶極子於元件中造成的影響進行量測，以撇除其他製程擾動所形成之干擾因素，並針對電偶極子不同之擾動模式，如單一電偶極子位置變化或整體電偶極子大小擾動、整體電偶極子位置擾動對元件的影響進行統計模擬的實驗。除此之外，我們提出了一個統計公式來預測當一批鰭狀場效電晶體元件之二氧化鉿/二氧化矽介面中電偶極子個數為帕松分佈時，其臨界電壓變化的分布及標準差可由此公式快速預測，或可反推求得元件中電偶極子之濃度分布。在本模擬實驗中考慮了三種不同尺寸之元件，以了解隨著元件的微縮下，電偶極子對元件的影響趨勢會有怎樣的衝擊，並針對各尺寸之元件進行一定量之模擬研究，以取得具代表性之實驗數據。最後，我們降低電偶極子濃度來做模擬實驗，以驗證公式之預測值在低電偶極子濃度的狀況下是否也符合實驗預期。

The random HfO2/SiO2 interface dipole in high-k metal-gate fin field-effect transistor (HKMG FinFET) is one of the important topics in semiconductor manufacturing, concerning the threshold voltage variation, device reliability and yield rate. In this work, through the help of modern 3-D technology computer aided design (TCAD) software, we can focus on the impact of dipole effect in devices, decouple other variability sources while manufacturing processes. Also, we can perform simulation tasks with different random configurations of HfO2/SiO2 interface dipole, for example, single dipole with different positions, random size of HfO2/SiO2 interface dipole and random placement of HfO2/SiO2 interface dipole. In addition to the simulation tasks, we also propose a new analytic statistical model to predict the threshold voltage distribution and its standard deviation, under the condition of random number of HfO2/SiO2 interface dipoles in HKMG FinFET. In this simulation work, we consider three different device scales to investigate the trend of dipole effect under the scaling of HKMG FinFET devices. Moreover, we lower the dipole density to suppress the impact of HfO2/SiO2 interface dipole effect, and examine if the model still matches with our expectation under low dipole density condition.

摘要 I
Abstract II
Acknowledgement III
Chapter 1 Introduction 1
Chapter 2 Single HK/IL Interface Dipole Effect with Different Dipole Positions 4
2.1 Introduction 4
2.2 Threshold Voltage Variation under One Single Dipole 4
2.3 Conclusion 5
Chapter 3 Threshold Voltage Variability Induced by the Random Size of HK/IL Interface Dipole 7
3.1 Introduction 7
3.2 Random Dipole Size Induced Threshold Voltage Variability 7
3.3 Conclusion 9
Chapter 4 Threshold Voltage Variability Induced by the Random Placement of HK/IL Interface Dipole 10
4.1 Introduction 10
4.2 Analytic Statistical Model 11
4.3 Random Dipole Placement Induced Threshold Voltage Variability 13
4.4 Conclusion 15
Chapter 5 Conclusion 17
References 19

[1] H. Ota, et al., "Intrinsic Origin of Electron Mobility Reduction in High-k MOSFETs - From Remote Phonon to Bottom Interface Dipole Scattering," IEDM Tech. Dig., pp. 65-68, 2007.
[2] A. R. Trivedi, et al., "A simulation study of oxygen vacancy-induced variability in HfO2/Metal Gated SOI FinFET," IEEE Trans. Electron Devices, vol. 61, pp. 1262-1269, 2014.
[3] X. Wang, et al., "Statistical Variability and Reliability in Nanoscale FinFETs," IEDM Tech. Dig, pp. 103-106, 2011.
[4] Z. C. Yang, et al., "Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation," Appl. Phys. Lett., vol. 94, no. 25, p. 252905, 2009.
[5] K. Kita, and A. Toriumi, "Intrinsic origin of electric dipoles formed at high-k/SiO2 interface," Proc. IEEE IEDM, pp. 1-4, 2008.
[6] S. H. Hsieh, et al., "A new microscopic formalism for the electron scattering by remote “paired” dipoles in HKMG MOSFETs," Proc. IEEE SISPAD, pp. 201-204, 2016.
[7] O. Sharia, et al., "Theoretical study of the insulator/insulator interface: Band alignment at the SiO2∕HfO2 junction," Phys. Rev. B, vol. 75, p. 035306, 2007.
[8] A. G. Van Der Geest, et al., "Ab initio study of the electrostatic dipole modulation due to cation substitution in HfO2/SiO2 interfaces," Phys. Rev. B, vol. 86, p. 085320, 2012.
[9] D. J. Frank, et al., "Monte Carlo modeling of threshold variation due to dopant fluctuations," Proc. VLSI Tech. Symp., pp. 169-170, 1999.
[10] A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET’s: A 3-D ‘atomistic’ simulation study," IEEE Trans. Electron Dev., vol. 45, no. 12, pp. 2505-2513, 1998.
[11] G. Roy, et al., "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Dev., vol. 53, no. 12, pp. 3063-3070, 2006.
[12] Y.-S. Wu, et al., "Investigation of switching-time variations for nanoscale MOSFETs using the effective-drive-current approach," IEEE Electron Device Lett., vol. 31, no. 2, pp. 162-164, 2010.
[13] C.-H. Lin, et al., "Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond," Proc. VLSI Tech. Symp., pp. 16-17, 2011.
[14] A. R. Brown, et al., "Impact of metal gate granularity on threshold voltage variability: A full-scale threedimensional statistical simulation study," IEEE Electron Device Lett., vol. 31, no. 11, pp. 1199-1201, Nov. 2010.
[15] H. Dadgour, et al., "Statistical modeling of metalgate Work-Function Variability in emerging device technologies and implications for circuit design," Proc. IEEE/ACM Int. Conf. Comput.-Aided Design, pp. 270-277, Nov. 2008.
[16] H. Dadgour, et al., "Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability," Proc. IEDM Tech. Dig, pp. 705-708, 2008.
[17] M. Kadoshima, et al., "Two different mechanisms for determining effective work function (Φm eff) on high-k-Physical understanding and wider tunability of Φm eff," Proc. IEEE Symp. VLSI Technol., pp. 180-181, 2006.
[18] C. L. Hinkle, et al., "Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt," Proc. VLSI Technol. Dig., pp. 183-184, 2010.
[19] Koji Kita, and Toriumi Akira, "Origin of electric dipoles formed at high-k/SiO2 interface," Appl. Phys. Lett., vol. 94, p. 132902, 2009.
[20] Li Qiang Zhu, et al., "Observation of Dipole Layer Formed at High-k Dielectrics/SiO2 Interface with X-ray Photoelectron Spectroscopy," Appl. Phys. Express, vol. 3, no. 6, p. 061501, 2010.
[21] K. Shimura, et al., "Positive and negative dipole layer formation at high-k/SiO2 interfaces simulated by classical molecular dynamics," Jpn. J. Appl. Phys., vol. 55, no. 4S, p. 04EB03, 2016.
[22] Y. Kamimuta, et al., "Comprehensive Study of VFB Shift in High-k CMOS-Dipole Formation, Fermi-level Pinning and Oxygen Vacancy Effect," IEDM Tech. Dig., pp. 341-344, 2007.
[23] J. Robertson, et al., "Fermi level pinning by defects in HfO2-metal gate stacks," Appl. Phys. Lett., vol. 91, no. 13, p. 132912, 2007.
[24] K. Tatsumura, et al., "Intrinsic correlation between mobility reduction and Vt shift due to interface dipole modulation in HfSiON/SiO2 stack by La or Al addition," IEDM Tech. Dig., pp. 1-4, 2008.
[25] K. McKenna and A. Shluger, "The interaction of oxygen vacancies with grain boundaries in monoclinic HfO2," Appl. Phys. Lett., vol. 95, p. 222111, 2009.
[26] L. Lin and J. Robertson, "Atomic mechanism of electric dipole formed at high-K: SiO2 interface," J. Appl. Phys., vol. 109, p. 094502, 2011.
[27] P. Toniutti, et al., "On the origin of the mobility reduction in n- and p-metal–oxide–semiconductor field effect transistors with hafnium-based/metal gate stacks," J. Appl. Phys., vol. 112, p. 034502, 2012.
[28] J. Borrel, et al., "Considerations on fermi-depinning, dipoles and oxide tunneling for oxygen-based dielectric insertions in advanced CMOS contacts," Silicon Nanoelectronics Workshop, pp. 140-141, 2016.
[29] C. Y. Lin, et al., "Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs," Thin Solid Films , vol. 620, pp. 30-33, 2016.
[30] TCAD Sentaurus, version G-2014.06, Synopsys, Mountain View, CA, USA, 2014.
[31] H.-S. Wong and Y. Taur, "Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's," Proc. IEEE IEDM, pp. 705-708, 1993.