類神經網路是一種極具吸引力的下世代電腦運算方式，其中扮演神經突觸角色的元件佔有相當重要的地位。基於蔡少棠(Leon Chua)於1971年所提出之憶阻器(memristor)的概念，許多兩端點的新興元件被廣泛的討論及研究，其中包括電阻式記憶體(RRAM)。其擁有單位面積小、操作速度快、低功耗…等特性，因此極具潛力作為一電阻式突觸之應用。雖然相對於以電晶體為主要結構的其他突觸元件，電阻式突觸元件擁有較為簡單的結構，但是於製程工藝與材料的選擇上仍然有相當大的討論空間。而在實際應用上，許多研究著力於改善電阻式突觸的非理想效應，特別是權重更新 (weight update) 的線性程度，研究指出較線性的權重更新在類神經網路運算中將達到較高的準確率。
在此篇論文中，我們對Ni/HfO2/TiO2/TiN非燈絲型的電阻式記憶體作為電阻式突觸應用做簡單的介紹。針對不同製程參數之元件，利用電流對電壓的量測以及脈衝波量測長期增益效果(Long-term potentiation)和長期減損效果 (Long-term depression)做比較。除此之外，基於實際應用在類神經網路的操作考量，相對於原本單一極性的連續輸入波，我們設計了任意組合之輸入波形並建立適當的量測程序，讓我們對此元件在脈衝波下的表現有更深入透徹的了解。我們更提出一個以電阻和電容為基礎的精簡電路模型。在直流電的模擬操作下，能成功再現電流對電壓曲線，也藉由觀察個別分壓對時間的改變，我們對於此雙層結構之電阻式記憶體，表現在電流對電壓曲線上的特徵有了更好的解釋。在脈衝波的模擬操作下，我們成功模擬出LTP和LTD的效果並重現任意組合之輸入波形的量測結果。更重要的是我們從其中發現電容的充放電在元件動態操作上的表現，佔有很重要的地位。
在此研究中，根據對元件特性的分析及了解，我們建立了準確的精簡模型，使其在模擬神經突觸的權重更新時與實際硬體結果更為符合，我們認為這將使未來陣列層級的模擬有更好的真實性。

Neuromorphic computing has been considered as an attracting next-generation computing paradigm. Thus, synaptic devices that play a critical role in neuromorphic computing are of great interest. Based on the memristor model proposed by Leon Chua in 1971, several two-terminal emerging devices have been widely discussed, including RRAM. RRAM is a promising synaptic device because of its 4F2 compact cell size, fast switching speed, low power consumption, etc. It has a very simple structure compare with other transistor-based devices, but the optimal process and material systems are still actively researched. In particular, numerous studies focus on improving the non-ideal effects of the RRAM device, especially the linearity of the weight update. These studies pointed out that more linearly weight update is favorable for achieving higher accuracy in neural networks.
In this thesis, we introduce a Ni/HfO2/TiO2/TiN structure, non-filamentary type RRAM, as an artificial electronic synapse. We utilize the basic DC I-V measurement and the pulse measurement of long-term potentiation (LTP) and long-term depression (LTD) to compare the devices fabricated under different conditions. Nevertheless, the identical and continuous stimuli used for LTP and LTD measurements are not generally applicable in the practical pulse operating scheme of neural networks. We design an arbitrary combination of the input signal and the measurement procedure to get a better understanding of the device operation at pulse schemes. Finally, we propose a RC-based compact circuit model, which is capable of reproducing the DC I-V curve. Moreover, through the analysis of the time evolution of internal voltage in the device, we provide a better explanation to several unique features in DC I-V curve of this bilayer device. Finally, we successfully simulate the LTP and LTD and reproduce the results of the arbitrary combination of the stimulations. In particular, we report that the charging and discharging of the capacitors play an important role in the dynamic of resistive switching.
In this study, we construct a new compact model for bilayer non-filamentary RRAM through comprehensive measurement and detailed understanding on device mechanism. The model reproduces DC and AC characteristics of weight update from the actual device. We expect that this model would assist accurate array- and system-level simulation for neural networks.

摘要 I
Abstract III
Acknowledgements V
Contents VI
Figure Captions VIII
Table List XV
Chapter 1 Introduction 1
1.1 Background 1
1.2 Memristor 2
1.2.1 Resistive Random-access Memory 2
1.2.2 Synaptic Application 7
1.2.3 Compact Circuit Model 8
1.3 Motivation 9
Chapter 2 ALD Bilayer RRAM 12
2.1 Introduction 12
2.2 Switching Mechanism 12
2.3 Switching Characteristic in Various Top Electrodes, Thickness and Doping Concentration of Dielectrics 14
2.4 Basic Synaptic Characteristics 17
2.5 Summary 20
Chapter 3 RRAM as a Synaptic Device 22
3.1 Introduction 22
3.2 Pulse Analysis 22
3.2.1 Read Pulse Set Up 23
3.2.2 Initial Current Investigation 26
3.3 Arbitrary Stimulation 28
3.4 Summary 30
Chapter 4 Compact Circuit Model of Bilayer Resistive Synaptic Device 32
4.1 Introduction 32
4.2 The Circuit Elements 33
4.3 DC I-V Characteristic Modeling 41
4.3.1 The Designation of the Function Form 43
4.3.2 Thickness Effect 45
4.3.3 Location of DC Current Minimum 46
4.4 AC Characteristic Modeling 49
4.4.1. Transient Effect from the Parasitic Capacitor 51
4.4.2. Parasitic Effect in Read 52
4.4.3. Operation under Various Current Level 57
4.5 Summary 58
Chapter 5 Conclusion and Future Prospect 60
5.1 Conclusion 60
5.2 Future Prospect 61
Reference 62
Vita 66
Publication List 67

[1] L. Chua, "Memristor-The missing circuit element," IEEE Trans. Circuit Theory, vol. 18, pp. 507-519, 1971.
[2] D. B. Strukov et al., "The missing memristor found," Nature, vol. 453, pp. 80-83, May, 2008.
[3] T. N. Theis and H. S. P. Wong, "The end of moore's law: A new beginning for information technology," Comput. Sci. Eng., vol. 19, pp. 41-50, Mar, 2017.
[4] E. Linn et al., "Beyond von Neumann--logic operations in passive crossbar arrays alongside memory operations," Nanotechnology, vol. 23, p.305205, Aug, 2012.
[5] J. Borghetti et al., "'Memristive' switches enable 'stateful' logic operations via material implication," Nature, vol. 464, pp. 873-876, Apr, 2010.
[6] C.-W. Hsu et al., "3D vertical TaOx/TiO2 RRAM with over 103 self-rectifying ratio and sub-A operating current," in IEDM, 2013, pp. 10.4.1-10.4.4.
[7] B. Hudec et al., "3D resistive RAM cell design for high-density storage class memory—a review," Science China Information Sciences, vol. 59, pp. 061403:1–061403:21, June, 2016.
[8] Z. Wang et al., "Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing," Nat. Mater., vol. 16, pp. 101-108, Jan, 2017.
[9] S. Park et al., "Nanoscale RRAM-based synaptic electronics: toward a neuromorphic computing device," Nanotechnology, vol. 24, p. 384009, Sep, 2013.
[10] J. Woo et al., "Improved synaptic behavior under identical pulses using AlOx/HfO2 bilayer RRAM array for neuromorphic systems," IEEE Electron Device Lett., vol. 37, pp. 994-997, Jun, 2016.
[11] W. Lian et al., "Approaches for improving the performance of filament-type resistive switching memory," Chin. Sci. Bull., vol. 56, pp. 461-464, 2011.
[12] H. S. P. Wong et al., "Metal-Oxide RRAM," Proc. IEEE, vol. 100, pp. 1951-1970, May, 2012.
[13] D. Kumar et al., "Enhancement of resistive switching properties in nitride based CBRAM device by inserting an Al2O3 thin layer," Appl. Phys. Lett., vol. 110, p. 203102, May, 2017.
[14] I. Valov et al., "Electrochemical metallization memories—fundamentals, applications, prospects," Nanotechnology, vol. 22, p. 289502, May, 2011.
[15] M. Hansen et al., "A double barrier memristive device," Sci. Rep., vol. 5, p. 13753, Sep, 2015.
[16] K. Baek et al., "In situ TEM observation on the interface-type resistive switching by electrochemical redox reactions at a TiN/PCMO interface," Nanoscale, vol. 9, pp. 582-593, Jan, 2017.
[17] X. L. Shao et al., "Electronic resistance switching in the Al/TiOx/Al structure for forming-free and area-scalable memory," Nanoscale, vol. 7, pp. 11063-11074, Jul, 2015.
[18] Y. F. Wang et al., "Characterization and modeling of nonfilamentary Ta/TaOx/TiO2/Ti analog synaptic device," Sci Rep, vol. 5, p. 10150, May, 2015.
[19] S. Yu et al., "Stochastic learning in oxide binary synaptic device for neuromorphic computing," Front. Neurosci., vol. 7, p. 186, 2013.
[20] S. Yu, D. Kuzum, and H.-S. P. Wong, "Design considerations of synaptic device for neuromorphic computing," in ISCAS, 2014, pp. 1062-1065.
[21] T. Chang, S. H. Jo, and W. Lu, "Short-term memory to long-term memory transition in a nanoscale memristor," ACS Nano., vol. 5, pp. 7669-76, Sep, 2011.
[22] S. R and I. M. Ovshinsky, "Analog models for information storage and transmission in physiological systems," Mater. Res. Bull., vol. 5, pp. 681-690, Aug, 1970.
[23] S. Boyn et al., "Learning through ferroelectric domain dynamics in solid-state synapses," Nat. Commun., vol. 8, p. 14736, Apr, 2017.
[24] S. Park et al., "Neuromorphic speech systems using advanced ReRAM-based synapse," in IEDM, 2013, pp. 25.6.1-25.6.4.
[25] S. N. Truong, S. J. Ham, and K. S. Min, "Neuromorphic crossbar circuit with nanoscale filamentary-switching binary memristors for speech recognition," Nanoscale Res. Lett., vol. 9, p. 629, Nov, 2014.
[26] F. Merrikh Bayat, B. Hoskins, and D. B. Strukov, "Phenomenological modeling of memristive devices," Appl. Phys. A., vol. 118, pp. 779-786, Jan, 2015.
[27] P. Sheridan et al., "Device and SPICE modeling of RRAM devices," Nanoscale, vol. 3, pp. 3833-3840, Sep, 2011.
[28] M. Hansen, M. Ziegler, and H. Kohlstedt, "Double barrier memristive devices for neuromorphic computing," in ICRC, 2016, pp. 1-8.
[29] S. Yu et al., "Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect," in IEDM, 2015, pp. 17.3.1-17.3.4.
[30] Z. Wang et al., "Engineering incremental resistive switching in TaOx based memristors for brain-inspired computing," Nanoscale, vol. 8, pp. 14015-14022, Aug, 2016.
[31] I. T. Wang, T. Chou, C. Li-Wen, C. Chih-Cheng, and H. Tuo-Hung, "Development of three-dimensional synaptic device and neuromorphic computing hardware," in ICSICT, 2016, pp. 620-623.
[32] X. Guan, S. Yu, and H. S. P. Wong, "On the switching parameter variation of metal-oxide RRAM－Part I: Physical modeling and simulation methodology," IEEE Trans. Electron Devices, vol. 59, pp. 1172-1182, Feb, 2012.
[33] M. J. Lee et al., "Electrical manipulation of nanofilaments in transition-metal oxides for resistance-based memory," Nano Lett., vol. 9, pp. 1476-81, Apr, 2009.
[34] C.-W. Hsu, " Non-linear resistive-switching memory for 3D ultra-high density storage-class memory applications," NCTU Thesis, 2015
[35] S. Dhar and A. H. Marshak, "Static dielectric constant of heavily doped semiconductors," Solid-State Electron., vol. 28, pp. 763-766, 1985.
[36] T.-P. Lin, "Numerical modeling of filamentart and non-filamentary RRAM," NCTU Thesis, 2015.
[37] H. Tang et al., "Electrical and optical properties of TiO2 anatase thin films," J. Appl. Phys., vol. 75, pp. 2042-2047, 1994.
[38] J. Woo et al., "Optimized programming scheme enabling linear potentiation in filamentary HfO2 RRAM synapse for neuromorphic systems," IEEE Trans. Electron Devices, vol. 63, pp. 5064-5067, Oct, 2016.
[39] J. Song et al., "Effects of RESET current overshoot and resistance state on reliability of RRAM," IEEE Electron Device Lett., vol. 35, pp. 636-638, Apr, 2014.
[40] P.-Y. Chen et al., "Mitigating effects of non-ideal synaptic device characteristics for on-chip learning," in ICCAD, 2015, pp. 194-199.
[41] S. Yu, X. Guan, and H. S. P. Wong, "Conduction mechanism of TiN/HfOx/Pt resistive switching memory: A trap-assisted-tunneling model," Appl. Phys. Lett., vol. 99, p. 063507, Aug, 2011.
[42] B. Gao et al., "Oxide-based analog synapse: Physical modeling, experimental characterization, and optimization," in IEDM, 2016, pp. 7.3.1-7.3.4.
[43] W. Li et al., "Giant dielectric constant dominated by Maxwell–Wagner relaxation in Al2O3/TiO2 nanolaminates synthesized by atomic layer deposition," Appl. Phys. Lett., vol. 96, p. 162907, 2010.
[44] W. Li et al., "Controllable giant dielectric constant in AlOx/TiOy nanolaminates," J. Appl. Phys., vol. 110, p. 024106, 2011.
[45] T. Chang, P. Sheridan, and W. Lu, "Modeling and implementation of oxide memristors for neuromorphic applications," in CNNA, 2012, pp. 1-3.
[46] Z. Jiang et al., "Verilog-A compact model for oxide-based resistive random access memory (RRAM)," in SISPAD, 2014, pp. 41-44.
[47] Z. Jiang et al., "A compact model for metal–oxide resistive random access memory with experiment verification," IEEE Trans. Electron Devices, vol. 63, pp. 1884-1892, 2016.
[48] P. Huang et al., "Compact model of HfO2-based electronic synaptic devices for neuromorphic computing," IEEE Trans. Electron Devices, vol. 64, pp. 614-621, 2017.