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研究生:吳冠勳
研究生(外文):Wu, Kuan-Hsun
論文名稱:電容式加速度計併讀取電路之單晶片設計
論文名稱(外文):Design of Monolithic Integrated MEMS Capacitive Accelerometer with Readout Circuit
指導教授:陳巍仁陳巍仁引用關係
指導教授(外文):Chen, Wei-Zen
口試委員:吳介琮謝志成
口試委員(外文):Wu, Jieh-TsorngHsieh, Chih-Cheng
口試日期:2017-11-03
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:中文
論文頁數:59
中文關鍵詞:加速度計
外文關鍵詞:Accelerometer
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摘要 I
ABSTRACT II
致謝 IV
目錄 V
圖目錄 VII
表目錄 X
第一章 簡介 1
1.1 背景與動機 1
1.2 組織架構 2
第二章 加速度偵測系統介紹 3
2.1 微機電 3
2.2 感測器讀取電路 8
2.2.1 消除直流偏移電壓以及低頻雜訊之電路 8
2.2.2 感測器讀取電路之分類[10] 12
第三章 電路設計與實現 14
3.1 整體電路介紹 14
3.2 控制訊號產生電路及偏壓電路 18
3.2.1 電路設計[12] 18
3.2.2 模擬結果 22
3.3 前置放大器 22
3.3.1 電路設計[26] 22
3.3.2 模擬結果 24
3.4 可調變增益放大器 26
3.4.1 電路設計 26
3.4.2 模擬結果 28
3.5 濾波器 30
3.5.1 電路設計[14][28][29] 30
3.5.2 模擬結果 39
3.6 直流伺服迴路 44
3.6.1 電路設計[20][21] 44
3.6.2 模擬結果 46
3.7 整體電路模擬 47
第四章 佈局與量測環境 52
4.1 晶片佈局 52
4.2 量測環境 54
第五章 結論 55
5.1 結論 55
5.2 未來工作 55
參考文獻 56
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