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研究生:張玟翔
研究生(外文):Chang, Wen-Hsiang
論文名稱:配電網絡設計方法為了加速實體設計的完成
論文名稱(外文):Power-Distribution-Network Design Methodologies toward Fast Physical-Design Closure
指導教授:趙家佐
指導教授(外文):Chao, Chia-Tso
口試委員:趙家佐劉建男吳凱強江蕙如林家民王廷基張世杰
口試委員(外文):Chao, Chia-TsoLiu, Chien-NanWu, Kai-ChiangJiang, Hui-RuLin, Jai-MingWang, Ting-ChiChang, Shih-Chieh
口試日期:2018-02-27
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:92
中文關鍵詞:配電網絡機器學習繞線成本模型電源網絡設計電遷移效應繞線驅策壓降配電網絡設計元件壓降
外文關鍵詞:power distribution networkPDNMachine-Learningrouting cost modelpower grid designEMrouting-drivenElectromigrationIR dropPDN designinstance IR drop
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隨著製程持續進步和設計複雜度持續增加,配電網絡(PDN)需要更多的繞線資源來滿足IR-drop和EM限制。在本論文中我們首先提出一個設計流程,用來在放置之前建立一個對繞線友善的PDN。這個設計流程考慮AP層的影響和PDN佈局配置的影響。接者,我們提出一個動態規劃的方法,用來最小化一個給定的均勻擺放的PDN在繞線上的影響,藉由在放置之後調整電源線的位置。實驗結果操作在40nm的微處理器上,顯示提出的設計流程和提出的動態規劃的方法,可以有效的產生一個對繞線友善的PDN,從而加速實體設計的完成。最後,我們提出一個設計流程,用來在放置之後,產生一個會讓全域/細部繞線總長差不多最小的PDN。此設計流程使用一個機器學習的模型,來快速的預測在給定一個PDN佈局配置下,其全域繞線的總長。實驗結果操作在28nm的工業設計上,顯示提出的設計流程,可以有效的產生一個對繞線友善的PDN,從而加速實體設計的完成。
As technology node keeps scaling and design complexity keeps increasing, power distribution network (PDN) require more routing resource to meet IR-drop and EM constraints. In this thesis, we first presented a design flow to build a routing-friendly PDN before placement. The design flow considers the impact of the aluminum-pad layer and the impact of PDN layout configurations. Second, we proposed a dynamic programming (DP) approach to further minimize the routing impact of a given uniform PDN by relocating the power stripes after placement. The results based on a 40nm microprocessor demonstrate that the proposed design flow and the proposed DP approach can effectively generate a routing-friendly PDN and in turn speed up the design closure at the physical-design stage. Finally, we propose a design flow to generate a PDN that can result in a near-minimal total wire length of global route (and in turn detailed route as well) after placement. The design flow uses a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration. Experiment results based on 28nm industrial block designs demonstrate that the proposed design flow can generate a routing-friendly PDN and in turn speed up the design closure at the physical-design stage.
Abstract (Chinese) i
Abstract (English) ii
Acknowledgement iii
Contents iv
1 Introduction 1
1.1 Overview 1
1.2 Designing a PDN before Placement 2
1.3 Relocating a Uniform PDN to Optimize Routing after Placement 4
1.4 Designing a PDN after Placement 5
2 Designing a Uniform Routing-Driven PDN before Placement 7
2.1 Design Environment 7
2.2 Layer Structure of Targeted PDN 7
2.3 Motivation of Proposed Design Flow 9
2.3.1 IR-Drop Map after Using the AP Layer 9
2.3.2 Impact of Power Stripe Layout Configuration on Routing 10
2.4 Overview of the Proposed Design Flow 12
2.5 Total Metal Width for Each Power Layer 14
2.5.1 Sufficient Total Metal Width of M8 Power Stripes 14
2.5.2 Sufficient Total Metal Width of M7 Power Stripes 18
2.5.3 Experimental Results 20
2.5.4 Additional Experiments 22
2.6 Layout Configuration of Power Stripes 24
2.6.1 Irredundant Stripe Width with Minimum Occupied Tracks 24
2.6.2 Routing Detour Caused by Power Stripes 28
2.6.3 Experiment of Finding Optimal Stripe Width 30
3 Relocating a Uniform PDN to Optimize Routing after Placement 32
3.1 Design Environment and Layer Structure of Targeted PDN 32
3.2 Motivation and Problem Formulation 32
3.3 Proposed Dynamic Programming Approach 34
3.4 Experimental Results 35
4 Designing a Uniform Routing-Driven PDN after Placement 38
4.1 Design Environment 38
4.2 Layer Structure of Targeted PDN 38
4.3 Concept of Irredundant Stripe Width 40
4.4 Motivation of Proposed Design Flow 41
4.4.1 Detailed Route Result as Routing Cost of a PDN 41
4.4.2 Total Metal Area of a PDN as Routing Cost of a PDN 41
4.4.3 Global Route Result as Routing Cost of a PDN 43
4.5 Overview of the Proposed Design Flow 44
4.6 Predicting Routing Cost with Machine Learning Techniques 46
4.6.1 Problem Formulation 46
4.6.2 Generating Training Samples and Predictor Features 47
4.6.3 Gaussian Process Regression 48
4.6.4 Information of Used Industrial Block Designs 50
4.6.5 Using Learned Model to Predict Global Route Results 52
4.6.6 Using Learned Model to Correlate Detailed Route Results 54
4.6.7 Introduction of Other Used Machine Learning Techniques 56
4.7 Searching Near-Optimal PDN Configuration 57
4.7.1 Proposed Searching Procedure 57
4.7.2 Experiments of Using Different PDN Design Flows 59
4.7.3 Effectiveness of the Proposed PDN Search Procedure 63
4.8 Using Different Training Samples or Different Pre-learning Processes 64
4.8.1 Overview 64
4.8.2 Using Different Sample # of Previous Designs 65
4.8.3 Using Different Sample # of the Targeted Design 67
4.8.4 Using Different Predictor Feature Sets 69
4.8.5 Using Different Predictor Feature Filters 72
4.8.6 Summary 74
5 Conclusion 75
6 Future Work 77
6.1 Designing a Nonuniform Timing-driven PDN after Placement 77
6.1.1 Design Environment and Layer Structure of Targeted PDN 77
6.1.2 Timing Impact of a PDN 78
6.1.3 Overview of the Proposed Design Flow 79
6.1.4 Generating the timing-related importance of each standard cell 80
6.1.5 Finding the PDN with Minimal Expected Timing Cost 81
6.1.6 Validating the nonuniform timing-driven PDN 83
6.2 Determining Layout Configurations for Via Array 84
Bibliography 88
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