臺灣博碩士論文加值系統

隨著摩爾定律的發展，在IC設計上我們遇到越來越多複雜困難的問題及更嚴苛的設計規則。其中壓降的問題一直是其中重要的一環。因為壓降的關係會導致雜訊容限的減少，以及增加的邏輯閘訊號的延遲。除此之外，供應電壓的大小一直隨著製程技術的縮減而變小。假若邏輯閘驅動電壓不夠，將會導致訊號完整性變差甚至造成功能的錯誤。因此相較於以前更需要去注重如何設計一個完善的電源供應網路。

在這篇論文中，我們提出了一個更有效的設計流程來自動生成電源供應網路，並且使用現時業界最新的工具來驗證我們的結果。我們改善先前的方法得到更完善的電源供應網路生成流程。首先，我們提出了新的分析模型來決定電源供應網路所需要的金屬量，裡面包含全部的電源供應資訊以及考慮不同硬體巨集的型別。另外，在我們優化的步驟裡使用的是非監督是學習的方法來鞏固我們的電源供應網路，藉此得到一個更適當的電源供應網路的拓樸。我們把此方法應用在實際的65奈米、0.18微米及40奈米的製程上，實驗結果證實我們的方法可以滿足給定的壓降條件並同時節省更多的金屬。

As the development of Moore's Law, many knotty problems come up and multiple design constraints need to be satisfied in IC design. The IR-Drop problem has been an important and serious issue for a long time. The voltage drop will reduce noise margin and increase gate delay; besides, the supply voltage of IC is much lower with the fast shrinking of CMOS process technology node. If the driving voltage of cell is not sufficient, it will deteriorate the signal integrity and cause functional failure. Therefore, a robust power distribution network that satisfies given constraints is more concerned than before.

In this thesis, we present a more effective design flow to automatically generate a power distribution network(PDN) verified by state-of-the-art commercial tool without IR violation. We improve the previous works to acquire a more comprehensive design flow to ensure the quality of our PDN. Firstly, we propose an analytical model which contains overall power metal resource and consider the different types of macros to determine the total metal width of PDN. Moreover, the optimization is based on a centroid learning method from unsupervised learning to consolidate PDN so that we can obtain a more adequate topology of PDN. Our work has experimented on real designs in 65 nm LP process, 0.18 um generic process, and 40 nm LP process. The results show that our framework can satisfy the given IR-Drop and simultaneously save lots of metal resource.

Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Previous Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Our Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 2 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Background of Power Distribution Network Model . . . . . . . . . . . . . . 4
2.2 Placing the Stripes Using the Cluster Method . . . . . . . . . . . . . . . 4
2.3 Sizing Power Distribution Network Using SLP . . . . . . . . . . . . . . . 6
Chapter 3 Overview of Proposed Design Flow . . . . . . . . . . . . . . . . . . 8
Chapter 4 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Construct Initial Power Distribution Network . . . . . . . . . . . . . . . 10
4.2 Power Distribution Network’s Optimization . . . . . . . . . . . . . . . . 15
Chapter 5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 ECC (TSMC 65 nm Process) . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 AES (TSMC 0.18 um Process) . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2.1 Experiment of Our Method and Method in [1] . . . . . . . . . . .. . . . 23
5.2.2 Comparison Between Different Distance Function . . . . . . . . . . . . . 27
5.3 DRAM Controller (TSMC 40 nm Process) . . . . . . . . . . . . . . . . . . . 31
Chapter 6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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