臺灣博碩士論文加值系統

當元件持續微縮下功率損耗成了嚴重的問題，降低次臨界擺幅來達到減少供給電壓可有效減少功率的消耗。本論文探討不改變傳輸機制的鐵電負電容場效電晶體。除了應用穩態下的Landau模型來模擬鐵電材料特性之外，一般不常考慮的動態項在高頻操作下就變得相當重要。文中將探討如何建立包含動態項的Landau模型並結合一般場效電晶體模型來模擬鐵電負電容場效電晶體在高頻下的特性和應用在電路中的表現。
本論文分成三個部份，第一部份是基本電性的分析。隨著負電容效應越強，次臨界擺幅越低，轉導最大值增加，轉導的範圍也變得集中。另外當鐵電負電容的值跟閘極電容接近時整體的電容值將會被放大。第二部份討論的是高頻特性，因為轉導跟閘極電容都同時被放大造成互相抵銷，所以負電容效應對截止頻率與最大震盪頻率的最大值影響並不明顯。但可以發現對應到截止頻率與最大震盪頻率的閘極電壓下降。負電容電晶體也只需較小的閘極電壓就可達到相同的功率轉換效率。在1dB壓縮點時之相同功率轉換效率下，負電容電晶體有較高的輸出功率跟增益，其對應到的閘極電壓範圍在0.6到0.8伏特。在功率轉換效率為10%時，增益跟輸出功率分別增加了1.42與1.2倍。第三部份是電路模擬。負電容電晶體具有很大的優勢特別在次臨界電壓下的邏輯應用，在供給電壓為0.3V時傳輸延遲改善了8.4倍。因為在相同電壓下負電容電晶體有較大的電流造成傳輸延遲大幅降低更有利於快速的操作。但當考慮了動態項阻尼係數的影響時，比本質電晶體有優勢的電壓範圍少了0.14伏特。在次臨界區域並較快的操作下，負電容電晶體可改善電壓轉移圖上的磁滯窗口。在較慢的操作下，使用負電容電晶體電壓轉移圖的斜率(反相器增益)也可增加1.4倍。我們使用的阻尼係數足夠小所以對電壓轉移特性的影響不大。此外在同樣的傳輸延遲表現下，負電容電晶體在次臨界區域會有較少的功率消耗。在傳輸延遲為0.18ns時，鐵電厚度為15nm時功率消耗可減少1.2倍。
鐵電材料需要很低的阻尼常數才有辦法達到高頻下的切換速度。我們從高頻與電路模擬發現並提出需求阻尼常數的期望值，以現有文獻上來看其值需要在降低兩個數量級才能減少並忽略其在高頻下造成的影響，並進一步能使負電容電晶體應用在GHz操作速度下的電路中。

As continuous downscaling the dimensions of MOSFET, the rapidly increasing power consumption has become a critical issue. Improving the subthreshold slope by overcoming Boltzmann limit can achieve VDD scaling. This thesis focus on ferroelectric negative capacitance FET which don’t change the transmission mechanism. Dynamic term in Landau model which rarely considered become quite important under high frequency operation. In this thesis, we discuss how to construct both static and dynamic state Landau model, then combine with compact MOSFET model to simulate NCFET’s RF characteristics and circuit performance.
In the first part of this work, we discuss basic electrical characteristics. As NC effect stronger SS become smaller, maximum value of gm increases, gm range become more concentrated. Besides, the total capacitance will be magnified when Cfe is close to Cmos. In the second part, high frequency characteristics are discussed. NC effect on maximum value of fT and fmax are not significant because the increase of capacitance and gm offset each other. But the relate VG for maximum value of fT and fmax become smaller. NCFET only needs less VG to achieve the same value of PAE. For same performance of PAE at P1dB, the correspond VG region from 0.6V to 0.8V has much higher Pout and gain in this work. At PAE=10%, gain and Pout improves 1.42 and 1.2 times respectively. In the last part, circuit performance is discussed. NC-inverter is beneficial especially for subthreshold logic application, the delay time improves 8.4 times at VDD=0.3V. For the same VDD in subthreshold region the NC-inverter has larger Ion thus delay time decreases, enabling faster operation. However, when considering damping effect, the superior region decrease about 0.14V. The hysteresis window circumstance in VTC can be improved using NC-inverter at subthreshold region for a fast sweep. For a slow sweep, the inverter gain of NC-inverter improves 1.4 times. NC-inverter has better VTC characteristic in subthreshold region for an appropriate small damping constant. Moreover, NC-inverter has less power consumption throughout subthreshold region at the same delay time performance. At delay time=0.18ns, NC-inverter of tFE=15nm power consumption can improves 1.2 times.
Ferroelectrics with low damping constant are necessary for high frequency switching. From both RF and circuit simulation, we give the requirement of damping constant value that need reduce two more order to let damping effect become insignificant, which can further make NCFET implement in high frequency (~gigahertz) circuit applications.

摘 要 i
Abstract iii
Acknowledgements v
Contents vi
Table Captions ix
Figure Captions x
Chapter 1 Introduction - 1 -
1.1　Limits to VDD Scaling - 1 -
1.1.1　Power Consumption Challenge to CMOS - 1 -
1.1.2　Methodology to Overcome Boltzmann Tyranny- 2 -
1.2 Ferroelectric Material - 4 -
1.3 Literature Review of Negative Capacitance Effect- 6 -
1.3.1　Quasi-Static State - 6 -
1.3.2　Dynamic State - 11 -
1.4 Motivation - 14 -
1.5 Scope and brief of the thesis - 15 -
Chapter 2 Basic NCFET Model Construction - 17 -
2.1　Methodology of Dynamic Simulation - 17 -
2.2　NCFET Modeling Approach - 19 -
2.3　RF Simulation Approach - 24 -
2.3.1　Two-port Network and S-parameter - 24 -
2.3.2　Unilateral Gain and H21 - 26 -
Chapter 3 Basic Transfer Characteristics of NCFET- 28 -
3.1　Model Parameters and Verification - 28 -
3.1.1　Extract Landau Parameters - 28 -
3.1.2　Verification of Negative Capacitance Effect- 30 -
3.2　Electrical Characteristic of NCFET - 31 -
3.3　Hysteresis Window in ID-VG - 34 -
Chapter 4 RF Characteristics of NCFET - 36 -
4.1　Cut Off Frequency and Maximum Oscillation Frequency - 36 -
4.1.1　NC Effect on fT and fmax Value - 37 -
4.1.2　fT and fmax variation versus VG - 39 -
4.1.3　Damping Effect on fT and fmax Value - 41 -
4.2　Harmonic Balance Simulation - 43 -
4.2.1　Power-Added-Efficiency - 43 -
4.2.2　1dB Compression Point - 44 -
4.2.3　NC Effect on Pout and Gain - 45 -
4.2.4　NC Effect on Power-Added-Efficiency - 47 -
Chapter 5 Circuit Performance of NCFET - 50 -
5.1　Inverter and Voltage Transfer Characteristic- 50 -
5.1.1　Subthreshold Operation for Logic Application- 52 -
5.1.2　Three-Stage-Inverter and Propagation Delay Time- 53 -
5.2　NC Effect on Inverter Performance - 54 -
5.2.1　NC Effect on Inverter Delay Time - 54 -
5.2.2 VTC Characteristic at Above Threshold Region- 56 -
5.2.3　VTC Characteristic at Subthreshold Region- 58 -
5.2.4　Damping Effect on Inverter Performance - 60 -
5.3　NC Effect on Energy and Power Optimization - 62 -
Chapter 6 Conclusion - 65 -
References - 67 -
個人簡歷 (Vita) - 71 -

[1]International Technology Roadmap for Semiconductors, 2011.
[2]A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329-337, Nov. 2011.
[3]K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” IEDM Tech. Dig, pp. 289-292. Dec. 2002.
[4]J. Müller et al., “Ferroelectricity in simple binary ZrO2 and HfO2,” Nano Lett., vol. 12, no. 8, pp. 4318-4323, July. 2012.
[5]Y. C. Chiu, C. H. Cheng, C. Y. Chang, Y. T. Tang, M. C. Chen, “Investigation of strain-induced phase transformation in ferroelectric transistor using metal-nitride gate electrode,” physica status solidi (RRL), vol. 11, no. 3, Mar. 2017.
[6]M. H. Lee et al., “Steep slope and near non-hysteresis of FETs with antiferroelectric-like HfZrO for low-power electronics,” IEEE Electron Device Lett, vol. 36, no. 4, pp. 294-296, Apr. 2015.
[7]S. Clima, D. J. Wouters, C. Adelmann, T. Schenk, U. Schroeder, M. Jurczak, and G.Pourtois, “Identification of the ferroelectric switching process and dopant-dependent
switching properties in orthorhombic HfO2: A first principles insight,” Appl. Phys. Lett, vol. 104, no. 9, 092906, 2014.
[8]S. Salahuddin, and S. Datta, “Can the subthreshold swing in a classical FET be lowered below 60 mV/decade?,” IEDM Tech. Dig, pp. 693-696, 2008.
[9]S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices,” Nano Letters, vol. 8, no. 2, pp. 405-410, Feb. 2008.
[10]M. Kobayashi, and T. Hiramoto, “Design Guideline for Steep Slope Ferroelectric FET Using Negative Capacitance in Sub-0.2V Operation: Operation Speed, Material Requirement and Energy Efficiency,” VLSI Tech. Symp, pp. 212-213, 2015.
[11]Landau, L. D. Khalatnikov, “I. M. On the anomalous absorption of sound near a second order phase transition point,” Dokl. Akad. Nauk, 96, 469-472, 1954.
[12]V. C. Lo, “Simulation of thickness effect in thin ferroelectric films using Landau Khalatnikov theory,” J. Appl. Phys, vol. 93, no. 5, pp. 3353-3359, Sep. 2003.
[13]Zhang, W.; Bhattacharya, K. “A computational model of ferroelectric domains. Part I: model formulation and domain switching,” Acta Mater, vol. 53, no. 1, pp. 185-198, Jan. 2005.
[14] A. I. Khan, K. Chatterjee, B. Wang, S. Drapcho, L. You, C. Serrao, S. R. Bakaul, R. Ramesh, and S. Salahuddin, “Negative capacitance in a ferroelectric capacitor,” Nature Materials, vol. 14, pp. 182-186, Feb. 2015.
[15]M. Kobayashi, and T. Hiramoto, “On device design for steep-slope negative-capacitance field-effect-transistor operating at sub-0.2V supply voltage with ferroelectric HfO2 thin film,” AIP Advances 6, 025113, 2016.
[16]Z. C. Yuan, S. Rizwan, M. Wong, K. Holland, S. Anderson, T. B. Hook, D. Kienle, S. Gadelrab, P. S. Gudem, M. Vaidyanathan, “Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs,” IEEE, vol. 63, no. 10, pp. 4046-4052, Sep. 2016.
[17]S. Sivasubramanian, A. Widom, and Y. Srivastava, “Equivalent circuit and simulations for the Landau–Khalatnikov model of ferroelectric hysteresis,” IEEE Trans. Ultrason., Ferroelectr., Freq. Control, vol. 50, no. 8, pp. 950-957, Aug. 2003.
[18]Y. Li, K. Yao, and G. S. Samudra, “Effect of ferroelectric damping on dynamic characteristics of negative capacitance ferroelectric MOSFET,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3636-3641, Sep. 2016.
[19]Y. Li, K. Yao, and G. S. Samudra, “Delay and Power Evaluation of Negative Capacitance Ferroelectric MOSFET Based on SPICE Model,” IEEE Trans. Electron Devices, vol. 64, no. 5, pp. 2403-2408, May. 2017.
[20]M. Kobayashi, N. Ueyama, K. Jang, and T. Hiramoto, “Experimental Study on Polarization-Limited Operation Speed of Negative Capacitance FET with Ferroelectric HfO2,” IEDM, 2016.
[21]S. Khandelwal, A. I. Khan, J. P. Duarte, A. B. Sachid, S. Salahuddin, and C. Hu, “Circuit Performance Analysis of Negative Capacitance FinFETs,” VLSI, 2016.
[22]Franz Sischka, “Characterization Handbook”
[23]T. C. Lim and G. A. Armstronga, ‘‘The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance,” Solid-State Electron, vol. 50, pp. 774-783, 2006.
[24]K. M. Chen, D. Y. Yang, and S. Y. Huang, ‘‘Effects of hot carrier stress and oxide breakdown on RF characteristics of MOSFETs,” APMC 2005 Proceddings, pp. 4-7, 2005.
[25]B. C. Paul, A. Raychowdhury, and K. Roy, ‘‘Device Optimization for Digital Subthreshold Logic Operation,” IEEE Trans. Electron Device, vol. 52, no. 2, pp. 237-247, Feb. 2005.
[26]S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, ‘‘Nanometer Device Scaling in Subthreshold Logic and SRAM,” IEEE Trans. Electron Device, vol. 55, no. 1, pp. 175-185, Feb. 2008.
[27]H. Fuketa, T. Yasufuku, S. Iida, M. Takamiya, M. Nomura, H. Shinohara, T. Sakurai, ‘‘
Device-Circuit Interactions in Extremely Low Voltage CMOS Designs (Invited),” IEDM, 2011.
[28]S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester, ‘‘Ultralow-voltage,minimum-energy CMOS,” IBM J. RES. & DEV, vol. 50, no. 4.5, pp. 469-490, July. 2006.