鎖相迴路用於產生穩定且具參考價值的時脈訊號，以便系統操作規律有秩序，作為電路心臟持續提供穩定之時脈訊號，近年來廣泛使用在SOC (System On Chip)應用上，更是攜帶式、通訊用等電子產品中不可或缺的角色。類比鎖相迴路已經有數十年的發展歷史，但是近年來為了能配合製程微縮以及降低晶片成本等考量下，數位式鎖相迴路電路之優點和需求逐漸被彰顯出來，展露出取代類比式之姿。
在本篇論文中，以全客戶式設計完成全數位鎖相迴路，第一顆晶片設計概念為跳脫傳統時間數位轉換器以串級方式依解析度大小處理的迷思，將不同解析度的時間數位轉換器採平行架構方式處理相位誤差，如此可縮短整體運算時間，並能達到節省功耗的效果。除此之外將數位控制振盪器加入相位內差的機制，可減少頻率的跳動以達到較精準的鎖定頻率，降低輸出訊號的抖動，設計採用週期線性的數位控制振盪器，振盪頻率範圍為273MHz~1110MHz。
第二顆晶片以第一顆晶片電路為基礎，加入外部可調式除頻器，使輸出訊號可鎖定至不同頻率，讓此鎖相迴路系統變得更為實用。再配合快速鎖定機制，電路一開始運作即可運算並跳至目標頻率附近，避免鎖定至不同頻率的時間差異過大，有效提升整體鎖相迴路的效能。
第一顆晶片輸出頻率鎖定至800MHz，量測結果包含1.51ps的方均根時間抖動(RMS Jitter)與7.56ps的峰對峰值時間抖動(Peak-to-Peak Jitter)，平均功率消耗為11.34mW，晶片核心面積為0.1mm2。而第二顆晶片模擬800MHz的平均峰對峰值時間抖動(Peak-to-Peak Jitter)為4.71ps，平均功率消耗為11.7mW，晶片核心面積為0.128mm2。

Phase-locked loops (PLL) generate a stable clock signal as a reference siganl to ensure circuits operate correctly. Nowadays, PLLs are widely used for SOC applications, such as wireless communication synthesizers, so it is indispensable in many applications. The analog phase-locked loop (APLL) has been developing for several years. However, in recent years, the all-digital phase-locked loop (ADPLL) has been gradually more mature, and it reveals its potential to replace the APLL.
In this thesis, we implement the ADPLL by using full-custom design flow. The design concept of the first chip is, instead of the traditional time-to-digital converter (TDC) using cascade architecture, using a parallel processing TDC to reduce the operation time and the dynamic power consumption. In addition, the digitally controlled oscillator (DCO), adopting the interpolated mechanism, can reduce the output frequency Jitter in order to achieve a more accurate locking frequency. The proposed DCO with a linearly periodic structure has the operation range from 273MHz to 1110MHz.
The design of the second chip, based on the first chip, adds an external adjustable divider so that the output signal can be locked to different frequencies. With the additional frequency tracking engine (FTE), the output can jump to the target frequency quickly to reduce the locking time. Therefore, the overall performance of the PLL is further improved.
The output frequency of the first chip is locked at 800MHz. The measurement results show the RMS Jitter of 1.51ps, the Peak-to-Peak Jitter of 7.56ps, average power consumption of 11.34mW, and the core area of 0.1mm2. While the second chip locks at 800 MHz, simulation results show the Peak-to-Peak Jitter of 4.71ps, average power consumption of 11.7 mW, and the core area of 0.128 mm2.

摘要 i
ABSTRACT iii
誌謝 v
目錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 鎖相迴路基本原理與架構 4
2.1 前言 4
2.2 類比式鎖相迴路 4
2.2.1 類比式鎖相迴路細部電路運作原理 5
2.2.2 類比式鎖相迴路模型分析 10
2.3 全數位式鎖相迴路 12
2.3.1 全數位式鎖相迴路細部電路運作原理 12
2.3.2 全數位式鎖相迴路模型分析 17
第三章 使用平行處理時間數位轉換器與相位內插數位控制振盪器之全數位鎖相迴路 18
3.1 前言 18
3.2 相位頻率偵測器與預判邏輯電路 (PFD & Prelogic) 20
3.3 平行處理時間數位轉換器 (Parallel Processing TDC) 22
3.3.1 粗調部分 (Coarse Tune) 22
3.3.2 次級部分 (Middle Tune) 23
3.3.3 細調部分 (Fine Tune) 25
3.4 數位迴路濾波器 (Digital Loop Filter) 28
3.5 相位內插數位控制振盪器 (Interpolated DCO) 35
3.5.1 相位內插架構 (Interpolated Architecture) 36
3.5.2 粗調延遲單元 (Coarse Delay Cell) 37
3.5.3 次級延遲單元 (Middle Delay Cell) 38
3.5.4 細調延遲單元 (Fine Delay Cell) 38
3.6 除頻器 (Divider) 39
3.7 鎖定偵測器 (Lock Detector) 40
第四章 具有外部可調式除頻器與快速鎖定機制之全數位鎖相迴路 44
4.1 前言 44
4.2 外部可調式除頻器 (Adjustable Divider) 44
4.3 快速鎖定機制 (Frequency Tracking Engine) 46
4.3.1 快速鎖定機制演算法 46
4.3.2 快速鎖定機制架構 48
4.3.3 具快速鎖定機制系統操作流程 50
第五章 量測與模擬結果 51
5.1 前言 51
5.2 使用平行處理時間數位轉換器與相位內插數位控制振盪器之全數位鎖相迴路模擬與量測 51
5.2.1 平行處理時間數位轉換器 51
5.2.2 時間放大器 53
5.2.3 相位內插數位控制振盪器 55
5.2.4 全數位鎖相迴路 56
5.2.5 量測考量 61
5.2.6 量測結果與晶片佈局、顯微圖 63
5.2.7 結果討論 68
5.3 使用平行處理時間數位轉換器與相位內插數位控制振盪器之快速鎖定全數位鎖相迴路模擬 70
5.3.1 全數位鎖相迴路 70
5.3.2 晶片佈局圖 81
5.3.3 結果討論 83
第六章 結論與未來展望 84
6.1 結論 84
6.2 未來展望 85
參考文獻 86

[1] 劉深淵與楊清淵, 鎖相迴路, 中華民國: 滄海書局, 2006
[2] Inchul Hwang, Soonsub Lee, Sangwon Lee, and Soowon Kim, ”A digitally controlled phaselocked loop with fast locking scheme for clock synthesis application,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp.168-169, Feb. 2000.
[3] P. Dudek, S. Szczepan’ski, and V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, Vol. 35, no. 2, pp.240-247, Feb. 2000.
[4] Kwang-Jin Lee, Seung-Hun Jung, Yun-Jeong Kim, Chul Kim, Suki Kim, Uk-Rae Cho, Choong-Guen Kwak, and Hyun-GeunByun, “A Digitally Controlled Oscillator for Low Jitter All-Digital Phase-locked Loops,” IEEE Asian Solid-State Circuit Conference, pp.365-368, Nov. 2005.
[5] Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, and Hong-June Park, “An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL,” IEEE Transactions on Circuits and Systems I, Vol. 56, no. 9, pp.2055-2063, Sep. 2009.
[6] P.-L. Chen, Ching-Che Chung, and Chen-Yi Lee, “A Portable Digitally Controlled Oscillator using Novel Varactors,” IEEE Transactions on Circuit and Systems II, Vol. 52, No. 5, pp.233-237, May 2005.
[7] H.-Y. Huang, J.-C. Liu, and K.-H. Cheng, “All digital PLL using Pulse-Based DCO,” IEEE International Conference on Electronics, Circuits and Systems, pp.1268-1271, Dec. 2007.
[8] Xin Chen, Jun Yang, and Xiao-ying Deng, “A Contribution to the Discrete Z-Domain Analysis of ADPLL,” IEEE International ASIC/SOC Conference, pp.185-188, Oct. 2007.
[9] Jianjun Yu, Fa Foster Dai, and Richard C. Jaeger, “A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology,” IEEE Journal of Solid-State Circuits, Vol. 45, No.4, pp.830-842, April 2010.
[10] Seon-Kyoo Lee, Young-Hun Seo, Hong-June Park, and Jae-Yoon Sim, “A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 45, no. 12, pp.2874-2881, Dec. 2010.
[11] V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions on Circuit and Systems II, Exp. Briefs, Vol. 54, no. 3, pp.247-251, Mar. 2007.
[12] R. B. Staszewski and P. T. Balsara, “Phase-domain all-digital phase-locked loop, ”IEEE Transactions on Circuit and Systems II, Exp. Briefs, Vol. 52, no. 3, pp.159-163, Mar. 2005.
[13] Yingchieh Ho, Yu-Sheng Yang, ChiaChi Chang, and Chauchin Su, “A Near-Threshold 480 MHz 78µW All-Digital PLL With a Bootstrapped DCO,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 11, Nov. 2013.
[14] Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, and An-Yen Wu, “A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm,” IEEE Transactions on Circuits and System, Vol. 57, No. 6, pp.430-434, June 2010.
[15] D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong, “A 0.3–1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller,” IEEE Journal of Solid State Circuits, Vol. 45, No. 11, pp.2300–2311, 2010.
[16] Hsuan-Jung Hsu, and Shi-Yu Huang, “A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 1, Jan. 2011.
[17] Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, and Shan-Chien Fang, “Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 12, pp.2240-2249, Dec. 2013.
[18] Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa, “A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration,” IEEE Journal of Solid-State Circuits, Vol. 49, No. 1, pp.50-60, Jan. 2014.
[19] Jung-Mao Lin, and Ching-Yuan Yang, “A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment,” IEEE Transactions on Circuits and Systems I, Vol. 62, No. 10, pp.2411-2422, Oct. 2015.
[20] Ching-Che Chung, Wei-Siang Su, and Chi-Kuang Lo, “A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 1, pp.408-412, 2016.