臺灣博碩士論文加值系統

隨著科技進步，運用在移動式裝置中的中央處理器需要擁有高速邏輯運算能力以及更高的可靠性和更高的穩定性，因此中央處理器的電力需求必須達到高效率、低耗能，使得中央處理器能有著更穩定的操作環境。因此運用在中央處理器的電壓轉換器需通常具備了動態電壓調節以及適應性電壓準位的技術，然而電壓轉換器在實現上述的技術下通常會增加額外的成本及面積。除此之外，由於中央處理器內含有多組核心，因此需要有多組電源供應器，在傳統架構中將高輸入電壓經由降壓轉換器降壓後再由多組的線性轉換器轉換成多組電源供應多組核心電壓，因為此架構以多組降壓轉換器以及多組的線性轉換器所組成，所以其功率轉換效率以及成本考量上並不佳，無法面對中央處理器嚴格的規範要求，因此本論文透過單電感多輸出轉換器配合多組的數位線性穩壓器來實現中央處理器的電壓供給模組。此電壓調節器第一級使用單電感多輸出調節器可以節省成本與面積，但由於先天的缺陷，單電感多輸出調節器會產生額外的輸出波紋，因此本架構在第二級轉換器中使用了數位線性穩壓器將多餘的電壓波紋濾除，除此之外利用了數位線性穩壓器的優點，使得能量耗損能最小化，並且透過數位控制、動態調適電壓和自適應調適電壓技術進一步調節整體電壓轉換器，進而優化了整體電壓供給模組的效能，以達到中央處理器的規範。

Owing to new technological advances, the central processor unit (CPU) used in mobile devices needs faster logic computing capability, higher reliability, and higher stability. In order to make the CPU operate in a stable environment, the power supply of the CPU requires high efficiency and low power consumption. Therefore, dynamic voltage identification (DVID) technique and adaptive voltage position (AVP) technique are usually implemented in the voltage regulator module (VRM) for the CPU. In addition, in conventional design, multiple DC-DC buck converters are used to provide multi-output voltage for the multi-cores of the CPU. However, this architecture is not suitable for the CPU because of the cost and area consideration. Consequently, a single inductor multi-output (SIMO) DC-DC converter becomes a good candidate due to the advantage of compact size and low cost. However, SIMO converter has larger output ripple and poor load variation response, which are not allowed by the CPU. As the result, each output of the SIMO converter needs to cascade a linear regulator to lower the output voltage ripple. However, due to the wide load range of CPU, the analog low-dropout (A-LDO) regulator requires larger dropout voltage, which degrades system power conversion efficiency. Therefore, the proposed VRM includes the SIMO converter and cascaded digital low-dropout (D-LDO) regulators which have low dropout voltage characteristic and thus lower the voltage ripple without degrading power conversion efficiency. Besides, the proposed VRM integrates AVP and DVID techniques as auto calibration dual-AVP (ACD-AVP) technique with the help of the D-LDO, thereby improving overall performance of the VRM under any load condition and OPPs.

摘 要 i
ABSTRACT ii
誌 謝 iii
Contents iv
Fig. Captions vi
Table Captions ix
Chapter 1 Introduction 1
1.1 Background of CPU power managements 2
1.2 The basic topologies of VR 3
1.2.1 Linear regulator 4
1.2.2 Digital Low-Dropout (DLDO) Voltage Regulator 5
1.2.3 Analysis 7
1.2.4 SWR 8
1.3 Techniques of CPU power managements 9
1.3.1 DynamicVoltage Identification(DVID) 9
1.3.2 Adaptive Voltage Positioning (AVP) 11
1.4 Single-inductor multi-output (SIMO) converters 13
1.4.1 Ripple issue 14
1.4.2 Load issue 15
1.5 Thesis Organization 16
Chapter 2 Prior Arts and Design Goals 17
2.1 The control methods of SIMO converter 17
2.1.1 Energy Delivery Paths of SIMO 19
2.2 Technique of the AVP droop control 22
2.2.1 AVP- / AVP+ control 25
2.2.3 DigitalAVPcontrol 29
2.3 Reduce Voltage-Guard-Band Technique and Dynamic Power Gating Control 30
2.4 The target of VRM design for the Multi-Core Processor 32
2.4.1 Lower the output voltage ripple 33
2.4.2 Improvement of Transient Response 34
2.4.3 Optimal system conversion efficiency 35
Chapter 3 The proposed VRM with DVID and Auto Calibration Dual-AVP technique 37
3.1 The architecture of proposed VRM 38
3.2 The concept of proposed ACD-AVP technique 39
3.3 The design parameter in ACD-AVP technique 47
3.3.1 Output impedance of the SITO converter 47
3.3.2 Rdroop 48
3.3.3 Digital AVP control 51
3.4 Circuit implement of the DVR 53
3.4.1 Clocked comparator 60
3.5 Circuit implement of the SITO converter 61
3.6 The proposed VRM process 63
3.6.1 Flow chart of proposed VRM 64
Chapter 4 Simulation Results 65
4.1 Chip layout 65
4.2 Simulation Results 66
5.2.1 Steady State 66
5.2.2 Transient enhancement 67
5.2.3 The DVID mode 69
Chapter 5 Conclusion and Future Work 71
5.1 Conclusion 71
5.2 Future work 71
Reference 72

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