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研究生:黃麒安
研究生(外文):Huang, Chi-An
論文名稱:使用台積電2P4M製程製作矽奈米線背閘極場效電晶體離子感測器
論文名稱(外文):Design of novel backside gate NWFET ion sensors using TSMC 2P4M process
指導教授:陳宗麟陳宗麟引用關係
指導教授(外文):Chen, Tsung-Lin
口試委員:黃正昇程登湖
口試委員(外文):Huang, Cheng-ShengCheng, Teng-Hu
口試日期:2018-03-30
學位類別:碩士
校院名稱:國立交通大學
系所名稱:機械工程系所
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:54
中文關鍵詞:台積電 0.35μm 2P4M 製程奈米線背閘極離子感測場效電晶體
外文關鍵詞:TSMC 0.35μm 2P4M processnanowireback-gateISFET
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傳統的離子感測晶片採用客製化的製程,需要浮動電極,因此價格昂貴。本研究探討採用商用製程(TSMC D35 2P4M process)來製作具背閘極(Backside Gate)的矽奈米線場效應電晶體(Nanowire Field Effect Transistor, NWFET)離子感測器的可行性,如獲成功,可一併解決「客製化製程」與「浮動電極」兩大問題。

在此NWFET的設計中,矽奈米線是使用D35製程中第二層的polysilicon,導入Sidewall Spacer Technique製備法來產生。另外,我們亦提出其他兩種類型的背閘極場效電晶體設計,用以比對、量化奈米線場效電晶體的感測能力。一種為在標準D35製程下所能製備的最小線寬(最窄通道)之背閘極場效電晶體;另一種為利用金屬層遮罩來定義通道寬度之之背閘極場效電晶體。為了確認所設計之元件具備傳統FET的性能,我們採用Sentaurus TCAD 模擬程式進行元件電性模擬。

實驗結果顯示,Sidewall Spacer Technique製備法可與D35製程整合製作出寬約170nm的矽奈米線,但是目前該奈米線會與其它層的polysilicon發生短路,以至於無法測得此元件特性。另一設計使用最小線寬設計的背閘極場效電晶體,雖然該設計的元件尺寸完全符合Design Rule的要求,但是元件通道仍在後製程的二氧化矽蝕刻過程中被破壞,因此亦無法測得元件特性。目前製作成功的是採用金屬層當遮罩所製備的背閘極場效電晶體,實驗結果顯示該元件確實具有離子濃度的感測能力。
Most conventional Ion-sensitive field effect transistor (ISFET) possessed a floating gate and took costly in-house process to fabricate. In this paper, we propose a method using TSMC D35 2P4M process to produce several backside gate nanowire field effect transistors (NWFET), in the expectation that both problems can be solved.

The silicon nanowire of our NWFET is formed with the second poly silicon layer in D35 process, it is produced by applying sidewall spacer technique. Another two designs of ISFET were fabricated in order to compare and quantify the sensing ability of NWFET. Of these two ISFETs, one of the poly silicon channel was designed based on the minimum linewidth permitted under D35 process design rules, while the other one’s linewidth was defined by depositing an extra Metal layer as a mask on top of the poly silicon layer. We use Sentaurus TCAD as our simulation tool to verify whether these designs show the characteristic of a conventional FET.

The result confirmed that a nanowire with aprrox. 170 linewidth can be successfully produced by applying sidewall spacer technique in D35 process. However, it is possible that the nanowires short-circuit the poly silicon from another layer, making their electrical characteristic unmeasurable . As for the comparison designs mentioned above, the ones with the minimal linewidth abide by the design rules lost all the FET channels during the post-process (RLS etching). The other ISFET that is fabricated by using the metal-masked method, on the other hand, functioned well comparing to other designs, and it also holds the ion sensing ability.
目錄
第1章 緒論..............................................1
1.1 研究動機.........................................1
1.2 製程介紹.........................................1
1.3 文獻回顧.........................................2
1.3.1 離子感測型FET介紹...............................2
1.3.2 矽奈米線FET介紹.................................6
1.3.3 FET元件之臨界電壓...............................12
1.4 論文架構.........................................15
第2章 晶片設計.........................................16
2.1 晶片設計架構....................................16
2.2 元件說明........................................18
2.2.1 FET元件設計- Design 1、4.......................18
2.2.2 FET元件設計- Design 2、5.......................20
2.2.3 FET元件設計- Design 3、6.......................22
第3章 FET電性模擬......................................25
3.1 模擬系統建構....................................25
3.1.1 模擬軟體簡介...................................25
3.1.2 模擬參數設置...................................25
3.2 模擬結果........................................27
第4章 晶片量測與PH感測實驗..............................35
4.1 晶片量測結果.....................................35
4.1.1 Sidewall Spacer Technique - Design 1、4........35
4.1.2 傳統製程- Design 2、5...........................41
4.1.3 金屬層遮蔽通道- Design 3、6.....................43
4.2 酸鹼感測實驗與結果...............................45
4.2.1 實驗方法.......................................45
4.2.2 酸鹼感測實驗結果................................46
第5章 結論與未來方向....................................49
5.1 結論............................................49
5.2 未來方向........................................49
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