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研究生:廖駿凱
研究生(外文):Chun-Kai Liao
論文名稱:使用拔靴帶式開關控制轉導放大器快速鎖定之鎖相迴路設計
論文名稱(外文):A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier
指導教授:郭可驥
指導教授(外文):Ko-Chi Kuo
學位類別:碩士
校院名稱:國立中山大學
系所名稱:資訊工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:中文
論文頁數:62
中文關鍵詞:相位頻率偵測器電荷幫浦鎖相迴路壓控振盪器拔靴帶式開關可控式轉導放大器
外文關鍵詞:PLLControllable OTAVCOCharge PumpPFDBootstrapped Switch
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本論文採用TSMC 90nm製程技術,在供應電壓1V下,提出了一個高調頻範圍與快速鎖定且除整數之頻率合成器。
此頻率合成器主要應用於IEEE 802.11ac Wi-Fi,提供4.243GHz至5.202GHz的本地振盪器。本論文所提出的頻率合成器包含相位頻率偵測器(Phase / Frequency Detector, PFD) 、低通迴路濾波器(Low Pass Filter, LPF)、電壓比較器(Comparator) 、可控式轉導放大器(Controllable Operational Transconductance Amplifier, C-OTA) 、電荷幫浦(Charge Pump, CP)、壓控振盪器(Voltage Control Oscillator, VCO)、拔靴帶式開關(Bootstrapped Switch)、非重疊電路(Non-overlapping Circuit)、上下計數器(Up/Down Counter)以及雙模計數器(Pulse-Swallow Counter)。
在此系統中,藉由比較V_ctrl,改變C-OTA的控制碼,以提升gm值和加大注入LPF之電流,進而達到快速鎖定之目的。
本論文提出之頻率合成器經模擬結果顯示功率消耗為9.48mW,鎖定時間為7.2μs,輸出頻率4.243GHz~5.202GHz。
The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning and fast locking CMOS integer-N frequency synthesizer. The synthesizer is mainly used for IEEE 802.11ac unlicensed band of Wi-Fi (Wireless Fidelity). It provides one ration frequency ranged from 4.243GHz to 5.202GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer contains a Phase / Frequency Detector, a Low Pass Filter , Comparator, Controllable Operational Transconductance Amplifier, a Charge Pump, a Voltage Control Oscillator, Bootstrapped Switch, Non-overlapping Circuit, Up/Down Counter, and a Pulse-Swallow Divider.
In order to speed up the lock time, the synthesizer increased the value of gm and the current injection into the LPF by comparing the V_ctrl and change the digital control code of C-OTA.
The simulation result of the synthesizer is shown that the power dissipation is 9.48mW, the output frequency is 4.243GHz~5.202GHz, the lock time is 7.2μs.
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織 1
第2章 基本架構介紹 2
2.1 鎖相迴路基礎觀念 2
2.2 鎖相迴路基礎架構與操作原理 3
2.2-1 相位頻率偵測器(Phase Frequency Detector, PFD) 3
2.2-2 電荷幫浦(Charge Pump, CP) 5
2.2-3 迴路濾波器(Loop Filter) 6
2.2-4 壓控振盪器(Voltage Control Oscillator, VCO) 7
2.2-5 除頻器(Frequency Divider) 9
2.3 加速鎖定類型鎖相迴路介紹 10
2.3-1 使用連續時間相位頻率偵測器快速鎖定技術於鎖相迴路 10
2.3-2 使用雙斜率相位頻率偵測器與電荷幫浦快速鎖定鎖相迴路 12
第3章 目標架構電路分析及實現 13
3.1 架構簡介 13
3.2 相位頻率偵測器(Phase/Frequency Detector, PFD) 16
3.3 電荷幫浦(Charge Pump, CP) 18
3.4 迴路濾波器(Loop Filter, LF) 22
3.5 壓控震盪器(Voltage Control Oscillator, VCO) 25
3.6 拔靴帶式開關(Bootstrapped Switch) 27
3.7 除頻器(Divider) 30
3.8 可控式轉導放大器(Controllable OTA) 33
3.9 電壓比較器(Comparator) 35
3.10 上/下計數器(UP/DN Counter) 37
3.11 非重疊電路(Non-overlapping Circuit) 38
第4章 目標架構電路之模擬 39
4.1 簡介 39
4.2 鎖相迴路各子電路之模擬 39
4.2-1 相位頻率偵測器 39
4.2-2 電荷幫浦 41
4.2-3 壓控震盪器 41
4.2-4 可控式轉導放大器 43
4.2-5 拔靴帶式開關 43
4.2-6 電壓比較器 44
4.2-7 上/下計數器 44
4.3 鎖相迴路系統模擬 45
第5章 目標電路模擬效能 47
5.1 效能比較 47
第6章 結論與未來展望 48
6.1 結論 48
6.2 未來展望 49
參考文獻 50
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