(3.237.97.64) 您好!臺灣時間:2021/03/04 15:19
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:郭家菱
研究生(外文):Jia-Lin Guo
論文名稱:用於功率因數修正之無橋交錯式降壓轉換器
論文名稱(外文):Bridgeless Interleaved Buck Converter for Power Factor Correction
指導教授:鄧人豪鄧人豪引用關係
指導教授(外文):Jen-Hao Teng
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:79
中文關鍵詞:無橋交錯式降壓轉換器數位平均電流控制交錯式降壓架構降壓型功率因數修正器功率因數修正
外文關鍵詞:Interleaved Buck ArchitecturePower Factor CorrectionBridgeless Interleaved Buck ConverterDigital Average Current ControlBuck Power Factor Corrector
相關次數:
  • 被引用被引用:0
  • 點閱點閱:117
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文的主要目的是研究主動式功率因數修正,在轉換器方面,本文提出一新型用於功率因數修正之無橋交錯式降壓轉換器,並以數位平均電流控制法分別控制輸入交流電之正負半週來達到功率因數修正。交錯式架構不只控制較簡單,也能在高輸出功率下有效降低元件的電流應力,改善功率元件高耐流、儲能電感體積過大、輸出電容過大等問題。本文實際製作一480W之無橋交錯式降壓轉換器,以驗證論文中所提之分析與設計考量是否合理。
不同於大部分的功率因數修正轉換器皆使用在升壓架構,本文所提之無橋交錯式降壓轉換器,可適用在較低電壓場合,能降低輸出電解電容值,減少成本,且也因為交錯式降壓架構,可應用於較大輸出功率的應用場合。經本文實際測試結果驗證本來所提架構之可行性,且輸入電流總諧波失真與功率因數皆符合國際規範。
This thesis studies the active power factor correction. In terms of converters, this thesis proposes a novel bridgeless interleaved buck converter for power factor correction, and uses digitalized average current control method to control the AC input voltage in positive half-cycle and negative half-cycle to achieve power factor correction. The interleaved architecture not only controls simplicity, but also can effectively reduce the component current stress at high output power, improve the high current resistance of the power components, the overlarge volume of the inductors, and the overlarge of output capacitors. This thesis actually produces a 480W bridgeless interleaved buck converter to verify whether the analysis and design considerations are reasonable.
Unlike most power factor correction converters, which are used in the boost architecture, the bridgeless interleaved buck converter proposed in this thesis can be used in lower voltage applications, can reduce the values of output electrolytic capacitor and reduce the cost, and also because of the interleaved buck architecture, it can be applied to applications with high output power. The feasibility of the proposed architecture is verified by the experimental results in this thesis, and the total harmonic distortion and power factor of the input current can meet the international specifications.
目錄
論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 1
1.3 論文大綱 2
第二章 功率因數修正與相關電路架構介紹 3
2.1 功率因數規範、定義、修正技術介紹與諧波失真定義 3
2.1.1規範 3
2.1.2功率因數與諧波失真定義 4
2.1.3功率因數修正器技術 9
2.1.4功率因數修正器控制方法 10
2.2 降壓型功率因數修正器 13
2.2.1傳統降壓型功率因數修正器 14
2.2.2雙相交錯式降壓型功率因數修正器 16
2.2.3無橋降壓型功率因數修正器 17
第三章 無橋交錯式降壓轉換器之架構與分析 19
3.1 無橋交錯式降壓轉換器之電路架構與分析 19
3.1.1功率開關責任週期大於0.5之動作模式分析 22
3.1.2功率開關責任週期小於0.5之動作模式分析 27
3.2 降壓型功率因數修正器損失估算 33
第四章 電路設計與控制 38
4.1 電路元件與參數設計 38
4.2 周邊電路設計 41
4.2.1功率開關驅動電路 41
4.2.2取樣電路 42
4.3 控制晶片與程式設計流程 46
第五章 電路測試規格與實驗結果 49
5.1 無橋交錯式降壓轉換器實測 50
5.2 電路損失分析 60
第六章 結論及未來展望 64
6.1 結論 64
6.2 未來展望 64
參考文獻 65
參考文獻
[1]梁適安,「交換式電源供給器之理論與實務設計(修訂版)」,台北:全華科技圖書股份有限公司,2008。
[2]P. N. Enjeti, R. Martinez, “A high performance single phase AC to DC rectifier with input power factor correction,” in Proc. IEEE APEC, San Diego, CA, pp. 190-195, Mar. 1993.
[3]B. Keogh, “Power Factor Correction Using the Buck Topology-Efficiency Benefits and Practical Design Considerations,” Texas Instruments, 2011.
[4]Y. Suzuki, T. Teshima, I Sugawara, A Takeuchi, “Experimental Studies on Active and Passive PFC Circuits,” in Proc. IEEE Telecommunications Energy Conference, Melbourne, VIC, pp.571-578, 1997.
[5]X. Lin, F. Wang, “New Bridgeless Buck PFC Converter with Improved Input Current and Power Factor,” in Proc. IEEE Transactions on Industrial Electronics, vol. 65, pp. 7730-7740, Feb. 2018.
[6]M. Mahdi, A. Ehsan, “Bridgeless single-phase step-down PFC converter,” in Proc. IET Power Electronics, vol. 9, pp.2631-2636, Nov. 2016.
[7]Z. Yang, S. Kiratipongvoot, C. K. Lee, “High Efficieney Bridgeless Power Factor Correction Buck Converter for High Frequency AC Systems,” in Proc. IEEE Energy Conversion Congress and Exposition, pp.1-7, Sept. 2016.
[8]W. Wang, D. D. Lu, G. M. Chu, “Digital control of bridgeless buck PFC converter in discontinuous-input-voltage-mode,” in Proc. IECON 2011-37th Annual Conference on IEEE Industrial Electronics Society, Melbourns, VIC, pp.1312-1317, Nov. 2011.
[9]Limit for Harmonic Current Emissions (Equipment Input Current <16A Per Phase), IEC/EN 61000-3-2, 1995.
[10]B Wilken, “Power Factor Correction and IEC555-2,” Power Techniques Magazine, pp.20-24, 1991.
[11]A. Prudenzi, U. Grasselli, “IEC Std. 61000-3-2 Harmonic Current Emission Limits in Practical Systems: Need of Considering Loading Level and Attenuation Effects,” in Proc. IEEE Power Engineering Society Summer Meeting, Vancouver, BC, vol. 1, pp. 277-282, Mar. 2001.
[12]宋自恆,林慶仁,功率因數修正電路之原理與常用元件規格,新電子科技雜誌第217期,2004。
[13]N. Mohan, T. M. Undeland, W. P. Robbins, “Power Electronics Converters Applications and Design, 3rd Edition,” John Wiley & Sons, 2003.
[14]T. Hoevenaars, K. LeDoux, and M. Colosino, “Interpreting IEEE Std 519 and Meeting its Harmonic Limits in VFD Applications,” in Proc. IEEE PCIC, Houston, TX, pp.145-150, Sept. 2003.
[15]W. M. Lin, M. M. Hernando, A. Fernandez, J. Sebastian, P. J. Villegas, “A new topology for passive PFC circuit design to allow AC-to-DC converters to comply with the new version of IEC1000-3-2 regulations,” in Proc. IEEE PESC, Cairns, Qld, vol. 4, pp. 2050-2055, Jun. 2002.
[16]W. Su, H. Ming, “Research and simulation of active power factor correction,” in Proc. IEEE CECNET, XianNing, China, pp. 5156-5158, Apr. 2011.
[17]Y. Geng, Y. Liu, J. Chen, P. Luo, “Analysis and design of a predictive CCM power factor correction converter,” in Proc. IEEE ICCCAS, Chengdu, vol. 2, pp. 398-401, Nov. 2013.
[18]B. Gandhi, M. Ezhilmaran, “Achieving high input power factor for DCM boost PFC converters by controlling variable duty cycle,” in Proc. IEEE ICCPEIC, Chennai, India, pp. 18-20, Apr. 2013.
[19]S. P. Yang, S. J. Chen, C. M. Huang, “Small-signal modeling and controller design of BCM boost PFC converters,” in Proc. IEEE ICIEA, Singapore, pp. 1096-1101, Jul. 2012.
[20]L. Rossetto, G. Spiazzi, P. Tenti, “Control Techniques for Power Factor Correction Converters,” in Proc. EPE International Power Electronics and Motion Control Conference, pp. 1310-1318, 1994.
[21]J. -S. Lai, D. Chen, “Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode,” in Proc. IEEE APEC Conference, San Diego, CA, pp. 267-273, Mar. 1993.
[22]Z. Yang, P. C. Sen, “Power factor correction circuits with robust current control technique,” in Proc. IEEE Transactions on Aerospace and Electronic Systems, vol 38, pp. 1210-1219, Oct. 2002.
[23]S. Chattopadhyay, K. Rajaganesh, V. Ramanarayanan, “Impedence Emulation Method for A Single Phase Shunt Active Filter,” in Proc. IEEE APEC Conference, Miami Beach, FL, vol. 2, pp. 907-912, Feb. 2003.
[24]S. Wall, R. Jackson, “Fast controller design for single-phase power factor correction systems,” in Proc. IEEE Transactions on Industrial Electronics, vol. 44, pp. 654-660, Oct. 1997.
[25]M. Orabi, T. Ninomiya, “A unified design of single-stage and two-stage PFC converter,” in Proc. IEEE Power Electronics Specialists Conference, Acapulco, Mexico, vol. 4, pp.1720-1725, Aug. 2003.
[26]C. A. Canesin, I. Barbi, “Analysis and design of constant-frequency peak-current-controlled high-power-factor boost rectifier with slope compensation,” in Proc. IEEE APEC, San Jose, CA, vol. 2, pp. 807-813, Mar. 1996.
[27]黃柏嘉,“用於功率因數修正之交錯式倍壓升壓型轉換器之研製”,國立中山大學電機工程研究所,中華民國105年8月。
[28]Y. C. Liu, T. Chen, P. J. Tseng, Y. K. Lo, H. J. Chiu, “DSP-Based Interleaved Buck Power Factor Corrector,” in Proc. 2014 International Power Electronics Conference, Hiroshima, Japan, pp.2810-2814, May. 2014.
[29]K. Arora, S. Katiyar, R. Patel, “Design and analysis of AC to DC converters for input Power Factor Correction,” in Proc. 2016 International Conference on Apploed and Theoretical Computing and Communication Technology, Bangalore, India, pp.171-176, July. 2016.
[30]F. Musavi, W. Eberle, W.G. Dunford, “A High-performance Single-phase Bridgeless Interleaved PFC Converter for Plug-in Hybrid Electric Vehicle Battery Chargers,” in Proc. IEEE Transactions on Industrial Applications, vol. 47, pp.1833-1843, Aug. 2011.
[31]陳育文,“交錯式降壓型功率因數修正器之研製”,國立台灣科技大學電子工程學系研究所,中華民國102年1月。
[32]B. A. Miwa, D. M. Otten, M. E. Schlecht, “High efficiency power factor correction using interleaving techniques,” in Proc. IEEE APEC, Boston, MA, pp. 557-568, Feb. 1992.
[33]Y. Jang, M. M. Jovanovic, “Bridgeless High-Power-Factor Buck Converter” in Proc. IEEE Transactions on Power Electronics, vol. 26, pp.602-611, Feb. 2011.
[34]F. Musavi, D. S. Gautam, W. Eberle, W. G. Dunford, “A simplified power loss calculation method for PFC boost topologies,” in Proc. IEEE ITEC, Detroit, MI, pp.1-5, Jun. 2013.
[35]F. Musavi, W. Eberle, W. G. Dunford, “Efficiency Evaluation of Single-Phase Solutions for AC-DC PFC Boost Converters for Plug-in-Hybrid Electric Vehicle Battery Chargers,” in Proc. IEEE Vehicle Power and Propulsion Conference, Lille, France, pp.1-6, Sept. 2010.
[36]K. Bernard, “Power Factor Correction Using the Buck Topology-Efficiency Benefits and Practical Design Considerations,” Texas Instruments, 2010.
[37]A.R. Sam, S. Franz, S. Ken, “PFC boost converter design guide,” Infineon, Feb. 2016.
[38]許育彰,“基於DSP控制之無橋電流饋入全橋式功率因數修正器研製”,國立台灣科技大學電子工程研究所,中華民國101年7月。
[39]符曉、朱洪順,“TMS320F2833X DSP應用開發與實踐”,北京航空航天大學出版社。
電子全文 電子全文(網際網路公開日期:20230803)
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔