(3.238.36.32) 您好!臺灣時間:2021/02/27 08:16
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:陳奕廷
研究生(外文):Chen, Yi-Ting
論文名稱:10位元200Ms/s 低功率脈管式類比數位轉換器
論文名稱(外文):A low power 10bit 200Ms/s Pipelined ADC
指導教授:徐永珍徐永珍引用關係
指導教授(外文):Hsu, Yung-Jane
口試委員:郭明清黃吉成
口試委員(外文):Kuo, Ming-ChingHuang, Ji-Chen
口試日期:2017-12-29
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:中文
論文頁數:82
中文關鍵詞:脈管式類比數位轉換器低功率類比數位轉換器
外文關鍵詞:Pipelined ADClow poweranalog-to-digital converter
相關次數:
  • 被引用被引用:0
  • 點閱點閱:196
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:55
  • 收藏至我的研究室書目清單書目收藏:0
隨著製程不斷進步,數位電路在運算處理能力與操作速度上發展迅速,並且能夠儲存大量的數位資訊,許多類比電路已逐漸改由位數電路的方式呈現,但是即使如此,電路與外界傳遞或接收資訊還是必須透過類比數位轉換器與數位類比轉換器來實現。為了實現低功率消耗且高速資料傳輸的電路,本研究使用包含前景式數位校正電路、Virtual Ground Reference Buffer、Switch Boostrapped…等等電路設計技巧來實現每秒取樣兩億次十位元脈管式類比數位轉換器,使的電路能夠在低功率消耗的情況下讓效能提高,以符合電子電路發展趨勢。

類比數位轉換器特性在輸入全擺幅正弦波,頻率為4.5 MHz 正弦波模擬結果能得到為雜訊位準-85 dB,訊號對雜訊及失真比61.6 dB。在供應電壓源為1.8伏特時所消耗的功率為68.5mW,另外,在輸入全擺幅正弦波,頻率為10 MHz 正弦波量測結果能得到為雜訊位準-40 dB,訊號對雜訊及失真比24.8 dB。晶片面積含I/O Pads 約為2.52 mm2,並採用TSMC 0.18μm 1P6M Standard CMOS製程加以實現並封裝。
A 10-bit 200-MS/s pipelined analog-to-digital converter (ADC) using virtual ground reference buffer and foreground calibration technique in TSMC 0.18μm standard CMOS process technology is presented.

The simulated ADC performances achieve -85 dB of Noise Level , 61.6dB of SNDR for 4.5MHz input signal. Under 1.8-V supply, the power consumption of the proposed ADC is 68.5-mW. The measured ADC performances achieve -40 dB of Noise Level, 24.8 dB of SNDR for 10MHz input signal. The chip area including I/O pads is 2.52 mm2.
摘要.............................................................1
Abstract.........................................................2
目錄.............................................................4
圖目錄...........................................................6
表目錄...........................................................9
第一章 前言.....................................................10
1.1 研究動機.................................................10
1.2 論文章節架構.............................................11
第二章 類比數位轉換器架構概論....................................12
2.1 類比數位轉換器的基本參數..................................12
2.2 類比數位轉換器架構介紹....................................15
2.2.1 快閃式類比數位轉換器......................................15
2.2.2 兩階式類比數位轉換器......................................17
2.2.3 脈管式類比數位轉換器......................................19
第三章 電路設計概論.............................................22
3.1 參考電壓緩衝器(Virtual Ground Reference Buffer)...........22
3.1.1 開迴路增益(open-loop-gain)..............................22
3.1.2 頻寬(bandwidth)........................................24
3.1.3 參考電壓緩衝器(Virtual Ground Reference Buffer)技術[2]....26
3.2 類比開關與其非理想效應....................................28
3.2.1 通道電荷注入(Charge injection)..........................28
3.2.2 時序饋入(Clock Feedthrough)............................29
3.2.3 開關阻值變化.............................................29
3.3 數位修正電路原理..........................................31
3.4 前景式數位校正電路原理....................................36
第四章 子電路分析與實現..........................................39
4.1 單級處理2.5位元之電路架構.................................39
4.2 Hybrid Cascode Compensation雙級放大器[6].................44
4.3 參考電壓緩衝器電路........................................51
4.4 比較器...................................................53
4.5 非重疊時序產生電路........................................58
4.6 偏壓電路.................................................59
4.7 脈管式類比數位轉換器整體效能模擬結果........................61
4.7.1 動態參數測試.............................................61
4.7.2 靜態參數測試.............................................66
4.7.3 模擬結果與文獻比較........................................67
第五章 晶片佈局與量測結果........................................68
5.1 晶片佈局.................................................68
5.2 量測環境.................................................71
5.3 量測結果.................................................72
5.4 分析與討論...............................................74
第六章 結論與未來展望...........................................78
6.1 結論....................................................78
6.2 後續研究建議.............................................79
參考文獻.........................................................81
[1] I. Ahmed, Pipelined ADC Design and Enhancement Techniques. 2010.
[2] H. H. Boo, D. S. Boning, and H.-S. Lee, "A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers," IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 2912-2921, 2015.
[3] 范振麟, 吳介琮, "用於管線式類比數位轉換器之數位背影校正技術," 國立交通大學, 電子工程研究所, 博士論文, 中華民國九十八年七月
[4] B. Razavi, Principles of Data conversion system design. 1995.
[5] B. Razavi, Design of Analog CMOS Integrated Circuit. 2001.
[6] B.-N. Fang and J.-T. Wu, "A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation," IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 670-683, 2013.
[7] P. Gholami and M. Yavari, "Digital Background Calibration with Histogram of Decision Points in Pipelined ADCs," IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, 2017.
[8] K. Iizuka, H. Matsui, M. Ueda, and M. Daito, "A 14-bit Digitally Self-Calibrated Pipelined ADC With Adaptive Bias Optimization for Arbitrary Speeds Up to 40 MS/s," IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 883-891, 2006.
[9] C.-J. Tseng, H.-W. Chen, W.-T. Shen, W.-C. Cheng, and H.-S. Chen, "A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC," IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1334-1343, 2012.
[10] M. Yavari, O. Shoaei, and F. Svelto, "Hybrid Cascode Compensation For Two-Stage Cmos Operational Amplifiers," IEEE International Symposium on Circuits and Systems, vol. 2, pp. 1565 - 1568, 2005.
[11] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, "Design-oriented estimation of thermal noise in switched-capacitor circuits," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 11, pp. 2358-2368, 2005.
[12] R. G. Carvajal et al., "The flipped voltage follower: a useful cell for low-voltage low-power circuit design," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1276-1291, 2005.
[13] 林哲輝, 徐永珍, "應用於影像處理之高效能低功率消耗10位元50MS/s脈管式類比數位轉換器," 國立清華大學, 電子工程研究所, 碩士論文, 中華民國九十八年七月
[14] T. Li, F. Li, and C. Zhang, "A 14bit 10MSps Low Power Pipelined ADC With 0.99pJ step FOM," 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, pp. 150 - 153, 2011.
[15] G. R, A. V. K, and B. Venkataramani, "A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology," 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 594-599, 2017.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔