跳到主要內容

臺灣博碩士論文加值系統

(44.211.31.134) 您好!臺灣時間:2024/07/22 18:02
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:葉昱宏
研究生(外文):Yeh, Yu-Hung
論文名稱:相容於 BCD 製程應用於高壓電路之內嵌式 可多次寫入記憶體
論文名稱(外文):BCD Process Embedded Multiple-Time Programmable Memory for High Voltage Circuits
指導教授:金雅琴
指導教授(外文):King, Ya-Chin
口試委員:林崇榮施教仁
口試委員(外文):Lin, Chrong-Jung
口試日期:2018-06-22
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:63
中文關鍵詞:BCD製程可多次寫入記憶體井耦合嵌入式記憶體
外文關鍵詞:BCDMTPwell-coupleembedded-memory
相關次數:
  • 被引用被引用:0
  • 點閱點閱:330
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
在這個萬物互連的時代,非揮發記憶體 (NVM) 扮演著重要的角色。非揮發記憶體 (NVM) 用途有:儲存預定程式碼、儲存組態資料與儲存使用者資料...等。為了讓產品提高競爭力,設計者把許多功能集中整合於單一晶片上(System on a Chip;SoC); 除了展現好的基本性能外,產品的體積、功耗、耐用度、多功能性..等將成為競爭力的要點,因此各項技術以及模組的整合勢必成為重要課題。
本論文提出一嵌入式可多次操作非揮發性記憶體,其特點為完全相容於 Bipolar/CMOS/DMOS高壓製程,此記憶元件將一浮動閘極 (Floating Gate) 覆蓋於兩個N型井作為耦合元件以及一用於讀取儲存於浮動閘極資料的讀取電晶體。通過設計浮動閘極覆蓋於N型井上的面積比,有效控制耦合元件與浮動閘極的耦合率 (Coupling Ratio)。藉由N型井耦合控制浮動閘極的電位可成功進行寫入與抹除的動作,而讀取時藉由控制一串聯於讀取電晶體的選擇電晶體閘極可進行讀取浮動閘極的狀態。
此嵌入式可多次操作非揮發性記憶體編程效率高,且在經過寫入抹除的循環測試後,仍然表現出優異的穩定性以及可靠性,並同時擁有良好的抗干擾特性;此外其低功耗操作以及良好的資料保存能力優點使此元件在高壓電路應用上具有相當的競爭力。
In this era of internet of things, non-volatile memory (NVM) plays an important role. The use of non-volatile memory (NVM) include: storing a predetermined code, storing configuration data, and storing user data...etc. In order to make products more competitive, many functions are integrated on a single chip (System on a Chip; SoC). In addition to having good performance, the compactness, functionality and durability, etc. also become index for product competitiveness. Considering cost and flexibility, each of integration is bound to become an important issue.

This study presents an embedded multi-time programmable non-volatile memory, fully compatible with the BCD high-voltage process. The memory element has a floating gate covering two N-wells as coupling nodes and a read transistor for accessing data stored in the floating gate. By designing the area ratio of the floating gate over the N-type well, the floating gate potential can be effectively controlled to allow erasing and programming. The storage data in the floating gate can then be read out through the BL current via a select transistor controlled by the wordline (WL).

This embedded multi-time programmable non-volatile memory has high programming efficiency, and still exhibits excellent stability and reliability after program-erase cycling stress. It also shows good program disturb immunity. In addition, its low-power operation and good data retention capabilities make this device competitive for application in CMOS HV circuits.
摘要 i
Abstract ii
致謝 iii
章節目錄 iv
附圖目錄 v
附表目錄 viii
第一章 序論 1
1.1 智慧型科技與嵌入式記憶體 1
1.2 邏輯製程下嵌入式非揮發性記憶體發展 2
1.3 Bipolar/CMOS/DMOS Process ( BCD 製程) 3
1.4 論文大綱 4
第二章 嵌入式非揮發性記憶體的技術挑戰 6
2. 1 嵌入式非揮發性記憶體簡介 7
2.1.1 MRAM 7
2.1.2 RRAM 8
2.1.3快閃記憶體 9
2.2 嵌入式浮動閘極記憶體介紹及應用機制回顧 10
2.2.1 浮動閘極記憶體載子注入機制回顧 10
2.2.2 單一複晶矽閘極記憶體元件論文回顧 13
2.2.3 單一複晶矽閘極記憶體元件比較 15
2.3 小結 16
第三章 相容於BCD製程應用於高壓電路的內嵌式可多次寫入記憶體 27
3.1 記憶體元件結構與陣列佈局規劃 27
3.2 記憶體元件操作機制 29
3.3 小結 31
第四章 記憶體元件量測結果與特性分析 36
4.1 記憶體元件操作特性分析 36
4.1.1 編程特性分析 36
4.1.2 抹除特性分析 38
4.1.3 讀取特性分析 38
4.2 記憶體元件可靠度分析 39
4.2.1 編程干擾 39
4.2.2 讀取干擾 40
4.2.3 元件耐久度 40
4.2.4 資料保存特性 41
4.3 小結 41
第五章 設計其他編程機制與最佳化探討 52
5.1 改用通道熱載子注入機制以及微編程修復機制 52
5.2 將其中一耦合元件改成利用P型耦合井 52
5.3 小結 53
第六章 總結 55
6.1 嵌入式可多次操作非揮發性記憶體優點分析 55
6.2 結語與未來展望 55
參考文獻 56
[1] Chang, J., Liao, H. J., Chih, Y. D., Sinangil, M., Chen, Y. H., Clinton, M., & Lu, S. L. L. (2017, June). Embedded memories for mobile, IoT, automotive and high performance computing. In VLSI Technology, 2017 Symposium on (pp. T26-T27). IEEE.
[2] Lu, Y. (2016, April). Ultra-low-energy IOT memory architectures based on embedded STT-MRAM. In VLSI Technology, Systems and Application (VLSI-TSA), 2016 International Symposium on (pp. 1-1). IEEE.
[3] Antonyan, A., Pyo, S., Jung, H., & Song, T. (2018, May). Embedded MRAM Macro for eFlash Replacement. In Circuits and Systems (ISCAS), 2018 IEEE International Symposium on (pp. 1-4). IEEE.
[4] Kim, M., Lee, J., Kim, Y., & Song, Y. H. (2018, February). An analysis of energy consumption under various memory mappings for FRAM-based IoT devices. In Internet of Things (WF-IoT), 2018 IEEE 4th World Forum on (pp. 574-579). IEEE.
[5] Do, N. (2016, May). eNVM technologies scaling outlook and emerging NVM technologies for embedded applications. In Memory Workshop (IMW), 2016 IEEE 8th International (pp. 1-4). IEEE.
[6] Park, S. K., Song, H. M., Kim, N. Y., Cho, I. W., & Yoo, K. D. (2014). Novel select gate lateral coupling single poly eNVM for an HVCMOS process. IEEE Electron Device Letters, 35(3), 351-353.
[7] Lee, Y. K., Moon, J. H., Kim, Y. H., Chun, M. J., Ha, S. Y., Choi, S., ... & Jung, E. (2008, May). 2T-FN eNVM with 90 nm logic process for smart card. In Non-Volatile Semiconductor Memory Workshop, 2008 and 2008 International Conference on Memory Technology and Design. NVSMW/ICMTD 2008. Joint (pp. 26-27). IEEE.
[8] Song, S. H., Kim, J., & Kim, C. H. (2014). A comparative study of single-poly embedded flash memory disturbance, program/erase speed, endurance, and retention characteristic. IEEE Transactions on Electron Devices, 61(11), 3737-3743.
[9] Chung, C. P., Chang-Liao, K. S., & Chen, C. Y. (2014). Enhanced performance of single poly-silicon EEPROM cell with a tungsten finger coupling structure by full CMOS process. IEEE transactions on Electron devices, 61(9), 3075-3080.
[10] Wang, Y., Xiang, J., Chen, X., Yang, T., Yan, N., & Min, H. (2015, October). A fully logic CMOS compatible non-volatile memory for low power IoT applications. In Internet of Things (IOT), 2015 5th International Conference on the (pp. 98-103). IEEE.
[11] Strum, A., Mahlen, T., & Roizin, Y. (2010, May). Non-volatile memories in the foundry business. In Memory Workshop (IMW), 2010 IEEE International (pp. 1-5). IEEE.
[12] Morris, D., Vaidyanathan, K., Lafferty, N., Lai, K., Liebmann, L., & Pileggi, L. (2011, June). Design of embedded memory and logic based on pattern constructs. In VLSI Technology (VLSIT), 2011 Symposium on (pp. 104-105). IEEE.
[13] Sitaram, A. R., Abraham, D. W., Alof, C., Braun, D., Brown, S., Costrini, G., ... & Gupta, A. (2003, June). A 0.18/spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications. In VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on (pp. 15-16). IEEE.
[14] Huang, S. C., Chen, K. H., Lin, W. Y., Lee, Z. L., Chang, K. W., Hsu, E., ... & Lu, C. (2012). Embedded I/O PAD circuit design for OTP memory power-switch functionality. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 746-750.

[15] Shen, R. S. J., & Hsu, C. C. H. (2004, July). Neobit/sup/spl reg//-high reliable logic non-volatile memory (NVM). In Physical and Failure Analysis of Integrated Circuits, 2004. IPFA 2004. Proceedings of the 11th International Symposium on the (pp. 111-114). IEEE.
[16] Lee, H. M., Woo, S. T., Chen, H. M., Shen, R., Wang, C. D., Hsia, L. C., & Hsu, C. H. (2006, February). Neoflash-true logic single poly flash memory technology. In Non-Volatile Semiconductor Memory Workshop, 2006. IEEE NVSMW 2006. 21st (pp. 15-16). IEEE.
[17] Park, N., Cha, J., Lee, K., Jeon, H., Choi, H., Kim, J., ... & Kang, H. (2009, June). aBCD18-An advanced 0.18 um BCD technology for PMIC application. In Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on (pp. 231-234). IEEE.
[18] Liu, K., Shen, Y., Ye, Y., & He, L. (2012, December). A current reference based on bandgap technology with wide input voltage range by using 0.18 µm BCD process. In Electron Devices and Solid State Circuit (EDSSC), 2012 IEEE International Conference on (pp. 1-2). IEEE.
[19] Huang, T. Y., Huang, C. H., Huang, C. F., Yang, C. Y., Yeh, W. C. V., Chu, H. P., ... & Gong, J. (2015, May). Demonstration of a HV BCD technology with LV CMOS process. In Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on (pp. 193-196). IEEE.
[20] Iwamoto, K., Kori, M., Terada, C., Doguchi, T., Mihara, M., Kasa, Y., ... & Tanaka, B. (2014, June). Advanced 300mm 0.13 μm BCD technology from 5V to 80V with highly reliable embedded Flash. In Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on (pp. 402-405). IEEE.

[21] Chang, M. F., Chiu, P. F., & Sheu, S. S. (2011, January). Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (pp. 197-203). IEEE Press.
[22] Marinissen, E. J., Prince, B., Keltel-Schulz, D., & Zorian, Y. (2005, March). Challenges in embedded memory design and test. In Design, Automation and Test in Europe, 2005. Proceedings (pp. 722-727). IEEE.
[23] Lee, J., Lee, K., Jung, I., Kim, H., An, H., Lee, T., & Lee, T. (2016, June). 0.13 μm modular BCD technology enable to embedding high density E2PROM, RF and hall sensor suitable for IoT application. In Power Semiconductor Devices and ICs (ISPSD), 2016 28th International Symposium on (pp. 419-422). IEEE.
[24] Hao, Y., Sim, P. C., Toner, B., Frank, M., Ackermann, M., Tan, A., ... & Liew, M. (2015, May). A 0.18 μm SOI BCD technology for automotive application. In Power Semiconductor Devices & IC's (ISPSD), 2015 IEEE 27th International Symposium on (pp. 177-180). IEEE.
[25] Na, K. Y., Baek, K. J., Lee, G. W., & Kim, Y. S. (2012). Simple embedded NVM cell for PMIC applications. Electronics Letters, 48(24), 1557-1559.
[26] Kimura, S. (2016, June). Advanced non-volatile embedded memory for a wide range of applications. In VLSI Technology, 2016 IEEE Symposium on (pp. 1-2). IEEE.
[27] Antonyan, A., Pyo, S., Jung, H., & Song, T. (2018, May). Embedded MRAM Macro for eFlash Replacement. In Circuits and Systems (ISCAS), 2018 IEEE International Symposium on (pp. 1-4). IEEE.
[28] Ahmed, K. A., Li, F., Lua, S. Y. H., & Heng, C. H. (2018). Area Efficient Multi-Bit per Cell Architecture for SOT-MRAM with Dedicated Diodes for High Density MRAM. IEEE Magnetics Letters.
[29] Seo, Y., & Roy, K. (2018). High-Density SOT-MRAM Based on Shared Bitline Structure. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[30] Gupta, N., Thakur, P., Dubey, S. K., & Islam, A. (2017, December). Design of nonvolatile MRAM bitcell. In Embedded Computing and System Design (ISED), 2017 7th International Symposium on (pp. 1-4). IEEE.
[31] Slaughter, J. M., Nagel, K., Whig, R., Deshpande, S., Aggarwal, S., DeHerrera, M., ... & Ikegawa, S. (2017, April). Spin-torque MRAM product status and technology for 40nm, 28nm and 22nm nodes. In Magnetics Conference (INTERMAG), 2017 IEEE International (pp. 1-1). IEEE.
[32] Fujita, S., Noguchi, H., Ikegami, K., Takeda, S., Nomura, K., & Abe, K. (2017, April). Novel memory hierarchy with e-STT-MRAM for near-future applications. In VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on (pp. 1-2). IEEE.
[33] Alioto, M. (2017, April). STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above. In VLSI Design, Automation and Test (VLSI-DAT), 2017 International Symposium on (pp. 1-1). IEEE.
[34] Gao, B., Kang, J., Chen, B., Huang, P., Ma, L., Zhang, F., ... & Yu, H. (2012, October). A novel self-selection bipolar RRAM cell with ultra-low operation currents for cross-point application. In Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on (pp. 1-3). IEEE.
[35] Kim, S., Jung, S., Kim, M. H., Cho, S., Lee, J. H., & Park, B. G. (2014, June). Switching and conduction mechanism of Cu/Si3N4/Si RRAM with CMOS compatibility. In Silicon Nanoelectronics Workshop (SNW), 2014 IEEE (pp. 1-2). IEEE.
[36] Kang, J. F., Gao, B., Huang, P., Li, H. T., Zhao, Y. D., Chen, Z., ... & Liu, X. Y. (2015, December). Oxide-based RRAM: Requirements and challenges of modeling and simulation. In Electron Devices Meeting (IEDM), 2015 IEEE International (pp. 5-4). IEEE.
[37] Chang, M. F., Chiu, P. F., & Sheu, S. S. (2011, January). Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. In Proceedings of the 16th Asia and South Pacific Design Automation Conference (pp. 197-203). IEEE Press.
[38] Ramaswamy, N. (2012, October). Challenges in Engineering RRAM technology for high density applications. In Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International (pp. 1-1). IEEE.
[39] Agin, J., Boyce, H., & Trexler, T. (2003, July). Overcoming test challenges presented by embedded flash memory. In Electronics Manufacturing Technology Symposium, 2003. IEMT 2003. IEEE/CPMT/SEMI 28th International (pp. 197-200). IEEE.
[40] Sako, M., Watanabe, Y., Nakajima, T., Sato, J., Muraoka, K., Fujiu, M., ... & Terada, Y. (2016). A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. IEEE Journal of Solid-State Circuits, 51(1), 196-203.
[41] Seo, Y., Song, M. Y., An, H. M., & Kim, T. G. (2013). A CMOS-process-compatible ZnO-based charge-trap flash memory. IEEE Electron Device Letters, 34(2), 238-240.
[42] Shum, D., Power, J. R., Ullmann, R., Suryaputra, E., Ho, K., Hsiao, J., ... & Tempel, G. (2012, May). Highly reliable flash memory with self-aligned split-gate cell embedded into high performance 65nm CMOS for automotive & smartcard applications. In Memory Workshop (IMW), 2012 4th IEEE International (pp. 1-4). IEEE.
[43] Tam, S., Ko, P. K., & Hu, C. (1984). Lucky-electron model of channel hot-electron injection in MOSFET's. IEEE Transactions on Electron Devices, 31(9), 1116-1125.
[44] Ong, T. C., Ko, P. K., & Hu, C. (1990). Hot-carrier current modeling and device degradation in surface-channel p-MOSFETs. IEEE Transactions on Electron Devices, 37(7), 1658-1666.
[45] Banerjee, S., Coleman, J., Richardson, B., & Shah, A. (1987, May). A band-to-band tunneling effect in the trench transistor cell. In VLSI Technology, 1987 Symposium on (pp. 97-98). IEEE.
[46] Lin, Y. H., Yeh, M. S., Jhan, Y. R., Chung, M. H., Chung, C. C., Yen, M., & Wu, Y. C. (2016). Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory. IEEE Transactions on Nanotechnology, 15(1), 80-84.
[47] Ashton, R. A. (1990, March). Gate oxide thickness measurement using Fowler-Nordheim tunneling. In Microelectronic Test Structures, 1991. ICMTS 1991. Proceedings of the 1991 International Conference on (pp. 57-60). IEEE.
[48] Ohsaki, K., Asamoto, N., & Takagaki, S. (1994). A single poly EEPROM cell structure for use in standard CMOS processes. IEEE Journal of Solid-State Circuits, 29(3), 311-316.
[49] Chi, M. H., & Bergemont, A. (1997, June). A new single-poly flash memory cell with low-voltage and low-power operations for embedded applications. In Device Research Conference Digest, 1997. 5th (pp. 126-127). IEEE.
[50] Roizin, Y., Pikhay, E., Dayan, V., & Heiman, A. (2009, May). High density MTP logic NVM for power management applications. In Memory Workshop, 2009. IMW'09. IEEE International (pp. 1-2). IEEE.
[51] Liang, M. S., Haddad, S., Cox, W., & Cagnina, S. (1986). Degradation of very thin gate oxide MOS devices under dynamic high field/current stress. In Electron Devices Meeting, 1986 International (pp. 394-398). IEEE.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top