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研究生:林執正
研究生(外文):Lin, Chih-Cheng
論文名稱:高速及高擺幅光通訊調變器驅動電路設計
論文名稱(外文):Design of High Speed and High Swing Modulator Drivers for Optical Communications
指導教授:徐碩鴻
指導教授(外文):Hsu, Shuo-Hung
口試委員:李明昌劉怡君
口試委員(外文):Lee, Ming-ChangLiu, Yi-Chun
口試日期:2018-07-13
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:英文
論文頁數:63
中文關鍵詞:調變器驅動電路光連結系統
外文關鍵詞:Modulator driverOptical interconnect system
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隨著資料傳輸與處理量日益增加,為了解決傳統金屬導線所造成的非理想效應,越來越多研究著手在光連結系統上。在此篇論文中,我們著重在設計超高速光通訊的前端驅動電路,希望能設計出傳遞40Gb/s訊號速度且達到輸出4伏特擺幅的調變驅動電路。第一章針對調變驅動電路的背景及設計難度作介紹,第二章則是統整了現今常用的各種寬頻技巧做深入的分析及介紹,第三章到第五章則是就實際下線的模擬及量測結果討論架構特性,第六章是就與工研院合作計劃中做的電路來介紹,最後在第七章作出結論。
第三章是運用傳統的調變驅動電路架構搭配低臨界電壓的電晶體實作於40 nm CMOS製程,由於臨界電壓需求較小相較於一般的RF MOS可利用較小的尺寸達到相同的放大倍率,因此藉由縮小寄生電容來放大頻寬,此電路中的電感皆是使用三維螺旋形電感,所以有極小的晶片面積0.620.53 〖mm〗^2。
第四章提出了為改善傳統電阻式負回授架構限制頻寬的問題,新設計的聯級擺幅補償架構的40 Gb/s調變器驅動電路,實作於90 nm CMOS 製程中,此架構雖然能夠達到較大的頻寬,但供應電壓必須設計在3.4/6.5V的情形下此電路消耗功率會提高到916 mW,而晶片面積0.870.97 〖mm〗^2。。
第五章則是進一步改良所提出的聯級擺幅補償架構電感peaking的方式,並增加了前級的pre-peaking stage,因此而能在維持輸出4〖.5V〗_PP的情況下進一步的增加頻寬,並且降低供應電壓致3.4/6 V,使得功耗降低至約為767.2mW。
第六章藉由與工研院合作的計畫嘗試了不同於一般的電路架構及製程做設計,分別是使用65 nm CMOS分散式放大器電路架構和130 nm SiGe HBT元件做設計,就模擬結果能達到更好的頻寬及輸出擺幅表現。最後在第七章作出結論及規格比較表。
With the rapidly increased demand of data rate for signal transmission, many researches put significant efforts on optical interconnects to solve the issues of speed limitation in conventional metal lines. In this thesis, we focus on designing ultra-high speed front-end circuits of optical communications to achieve a 40Gb/s modulator driver with 4V_PP output swing. The first chapter shows the challenges and background of modulator driver design. The second chapter lists the common broadband techniques and some detailed analysis. The third to fifth chapters show the simulation and measurement results of the circuits. The sixth chapter introduces two circuits with ITRI’s project. And a conclusion is given in chapter seven.
In chapter 3, a low-Vt MOS is employed in a conventional topology of modulator driver in 40 nm CMOS. Due to the lower voltage requirement, those low-Vt MOS transistors can achieve the same gain but with smaller sizes, and further broaden the bandwidth. The chip area is 0.620.63 μm2 including two 3D solenoid inductors.
In chapter 4, a new circuit topology is proposed based on cascade swing compensation to alleviate the bandwidth limitation from the conventional topology. The circuit is realized in 90 nm CMOS process. With the relatively large supply voltage of 3.4/6.5 V, the power consumption increased to 916 mW with a chip area of 0.870.97 m2.
In chapter 5, a further modified broadband technique with cascade swing compensation topology is designed. Based on measurement results, a 4.5 V_PP output swing is achieved with a 767.2 mW power consumption, and the chip area is 0.870.97 〖μm〗^2.
In chapter 6, two different types of modulator drivers were proposed due to the cooperation project with ITRI. The first circuit topology is distributed amplifier (DA) which is fabricated in 65 nm CMOS process. With the series of inductors between each stages all parasitic capacitances can be merged as a transmission line connections. That reduces input and output poles, then broaden bandwidth. The other circuit was fabricated with 130 nm SiGe HBT from IHP. By using the advantages of high f_T and high breakdown voltage characteristics of the device, the circuit can obtain a much better performance with high speed and high output swing. But a series of buffer stages are necessary to prevent the leakage current from base node during large signal transmission.
And the final conclusion and specification comparison table with the presented papers are introduced in chapter 7.
CONTENTS
ABSTRACT iii
摘要 v
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xi
Chapter1 INTRODUCTION 1
1.1 Background and motivation 1
1.2 Introduction to Modulator driver 3
1.3 Design consideration of modulator driver 4
Chapter2 INTRODUCTION AND DESIGN OF BROADBAND TECHNIQUES 7
2.1 Peaking skills 7
2.2.1 Shunt peaking inductor 7
2.2.2 T-coil peaking 8
2.2.3 Π peaking 9
2.2.4 Negative capacitance 10
2.2.5 Reversed Triple Resonance Network 11
2.2.6 π-resonant Network 13
2.3.1 Design Considerations of Inductor 14
2.3.2 Inductor equivalent model 15
2.3.3 Inductor loss 16
2.3.4 Pattern ground shield 17
2.3.5 GCPW transmission line 18
2.3.6 Summary 18
Chapter3 DESIGN OF MD WITH CONVENTIONAL TOPOLOGY IN 40 NM LOW-VT CMOS 19
3.1 Proposed structure 19
3.2 Low-Vt MOSFET 20
3.3 Proposed Two-Stage Modulator Driver 21
3.3.1 Second Order Active Feedback 22
3.3.2 Cascode Output Stage with Transistor Protection 23
3.4 Measurement Results and Conclusion 26
Chapter4 MODULATOR DRIVER WITH CASCADE SWING COMPENSATION IN 90 NM CMOS 29
4.1 Proposed structure 29
4.2 Conventional output stage 30
4.3 Cascade compensation output stage 31
4.4 Simulation and Measurement Results 33
Chapter5 DESIGN OF 40 Gb/S MD WITH REVISED CSC TOPOLOGY IN 90 NM CMOS 36
5.1 Proposed structure 36
5.2 Conventional output stage 37
5.3 Circuit analysis 39
5.4 Simulation and Measurement Results 44
Chapter6 DESIGN OF MODULATOR DRIVERS FOR HIGH SPEED AND HIGH OUTPUT SWING 50
6.1 Distributed Amplifier (DA) structure 51
6.2 IHP 130nm SiGe HBT 54
Chapter7 CONCLUSION AND FUTURE WORK 59
REFERENCES 62
REFERENCES
[1] I. Young, E. Mohammed, J. Liao, A. Kern, S. Palermo, B. Block, M. Reshotko, and P. Chang, “Optical I/O technology for tera-scale computing,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), ISSCC Dig. Tech. Papers, Feb. 2009, pp. 468–469.
[2] C. C. Tang, C. H. Wu, and S. 1. Liu, “Miniature 3D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, pp. 471-480, April 2002.
[3] C. Knochenhauer, J. C. Scheytt and F. Ellinger, "A Compact, Low-Power 40-GBit/s Modulator Driver With 6-V Differential Output Swing in 0.25- $mu$m SiGe BiCMOS," in IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1137-1146, May 2011.
[4] K. Schneider et al., “Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation,” IEEE Trans. Microw. Theory Techn., vol. 53, no. 11, pp. 3378–3387, Nov. 2005.
[5] J. Kim, J. F. Buckwalter, "A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS," IEEE J. Solid-State Circuits, vol.47, no.3, pp.615,626, March 2012
[6] D.U. Li and C.M. Tsai, “10-Gb/s modulator drivers with local feedback networks,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1025–1030, May 2006.
[7] S. Galal, B. Razavi, "10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol.38, no.12, pp.2138,2146, Dec. 2003
[8] M. S. Kao, F. T. Chen, Y. H. Hsu and J. M. Wu, "20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 475-483, March 2014.
[9] V. Radisic et al., "40 Gb/s differential traveling wave modulator driver," in IEEE Microwave and Wireless Components Letters, vol. 13, no. 8, pp. 332-334, Aug. 2003.
[10] S. Nakano, M. Nogawa, H. Nosaka, A. Tsuchiya, H. Onodera and S. Kimura, "A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking," 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, 2015, pp. 1-4.
[11] C. Y. Hsiao, T. Y. Su, and S. S. H. Hsu, “CMOS distributed amplifiers using gate-drain transformer feedback technique,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 8, pp. 2901–2910, Aug. 2013.
[12] A. Fatemi, H. Klar and F. Gerfers, "Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 2387-2390.
[13] P. Rito et al., "A 40 Gb/s 4 Vpp IQ modulator driver in 0.13 µm SiGe:C BiCMOS technology for 25 Ω Mach-Zehnder Modulators," 2015 IEEE MTT-S International Microwave Symposium, Phoenix, AZ, 2015, pp. 1-4.
[14] S. Nakano et al., “A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking,” Proc. IEEE Asian Solid-State Circuits Conf., 2015, pp. 1–4.
[15] Y. F. Li, P. W. Chiu, K. Li, D. J. Thomson, G. T. Reed and S. S. H. Hsu, "A 40-Gb/s 4-Vpp Differential Modulator Driver in 90-nm CMOS," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 1, pp. 73-75, Jan. 2018.
[16] I. García López et al., "A 40 Gb/s PAM-4 monolithically integrated photonic transmitter in 0.25 µm SiGe:C BiCMOS EPIC platform," 2017 IEEE 17th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, 2017, pp. 30-32.
[17] P. Rito, I. G. Líópez, A. Awny, A. C. Ulusoy and D. Kissinger, "A DC-90 GHz 4-Vpp differential linear driver in a 0.13 μm SiGe:C BiCMOS technology for optical modulators," 2017 IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, 2017, pp. 439-442.
[18] G. Yang, Z. Wang and K. Wang, "Modified T-Model With an Improved Parameter Extraction Method for Silicon-Based Spiral Inductors," in IEEE Microwave and Wireless Components Letters, vol. 24, no. 11, pp. 817-819, Nov. 2014.
[19] Yen-Ying Liu (劉彥廷), “Design of Ultra-High Speed Front-End Circuits for Optical Communication (超高速光通訊前端電路設計),”國立清華大學電子工程研究所碩士論文,2014。
[20] Po-Chun Wang (王柏鈞), “Design of High Speed Transmitters for Optical Communications (高速光通訊傳輸端電路設計),”國立清華大學電子工程研究所碩士論文,2015。
[21] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”.
[22] Behzad Razavi, “Design of ICs for optical Communications”.
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