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研究生:翁槐懋
研究生(外文):Weng, Hui-Mao
論文名稱:用於即時交通標誌辨識的高資源效能之硬體實作
論文名稱(外文):Resource Efficient Hardware Implementation For Real-Time Traffic Sign Recognition
指導教授:許雅三
指導教授(外文):Hsu, Yar-Sun
口試委員:邱瀞德鐘太郎
口試委員(外文):Chiu, Ching-TeJong, Tai-Lang
口試日期:2017-09-07
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2017
畢業學年度:106
語文別:英文
論文頁數:74
中文關鍵詞:路標辨識
外文關鍵詞:Traffic sign recognition
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近年來,車載電子成為一個熱門的領域。其中的駕駛輔助系統 (Advanced Driver Assistance System, ADAS) 更是現代車輛中常見的配備。交通標誌辨識則是駕駛輔助系統其中一項可以改進的技術。
針對交通標誌辨識中最重要的議題,也就是即時性與節約資源,本論文提出一個高效的硬體架構以達到這些目標。即時性是任何車載系統的首要條件,只有速度夠快才得以應對道路上多變的情況。另一方面,一個設計良好的系統必須節約能源的使用並有較低的成本,也就是必須節省資源。
在本論文中,交通標誌辨識採用兩階段的方法,分別為偵測與識別。在交通標誌偵測的階段,我們採用色域標準化轉換 (Normalized RGB Transform),再以單次連通性分析 (Single-Pass Connected Component Labeling) 尋找可能為標通標誌的區域。在交通標誌識別的階段,我們採用方向梯度直方圖 (Histogram of oriented gradient, HOG) 得出區域的特徵向量,再以支持向量機 (Support Vector Machine, SVM) 進行分類識別。此交通標誌辨識方法使用GTSDB的資料進行測試,得到96.61%的偵測率與90.85%的辨識率。
在硬體實作上,我們提出的架構節省了連通性分析所需的記憶體大小、簡化了方向梯度直方圖的計算複雜度。於典型條件下,CCL的主要記憶體比最先進的設計減少20%的大小。使用TSMC 90nm的製程下,提出的硬體操作頻率為105MHz,每秒可處理135張1360x960大小的影像。晶片面積約為1mm2且功耗僅約8mW,因此達到了即時性與節約資源的要求。
Recently, car electronic systems become more popular. Advanced Driver Assistance System (ADAS) is a common device in modern cars. Traffic sign recognition (TSR, or Road Sign Recognition, RSR) is one of the ADAS techniques that can be improved.
To concern the most important issues, which are real-time and computational resources, we propose a high efficiency hardware implementation for traffic sign recognition. Real-time is a restriction for any car electronic systems. Only fast systems are able to react to the changing traffic conditions. Furthermore, a well-designed system should be energy saving as well as low cost, which means resource efficiency.
In this work, we divide the TSR into two stages, detection and recognition. In the detection stage, we use Normalized RGB color transform and Single-Pass Connected Component Labeling (CCL) to find the potential traffic signs. In the recognition stage, Histogram of Oriented Gradient (HOG) is used to generate the descriptor of the signs, and we classify the signs with Support Vector Machine (SVM). The proposed method achieves 96.61% detection rate and 90.85% recognition rate while testing with GTSDB dataset.
Our hardware implementation reduces the storage of CCL, and simplifies the HOG computation. Main CCL storage size is reduced by 20% comparing to the most advanced design under typical condition. By using TSMC 90nm technology, the proposed design operates at 105 MHz clock rate and processes in 135 fps with image size of 1360x960. The chip size is about 1mm2 and power consumption is close to 8mW. Therefore, this work is resource efficient and achieves real-time requirement.
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Goals and Contributions 2
1.3 Thesis Organization 3
Chapter 2 Related Work 4
2.1 Overview 4
2.2 Image-Processing (Traditional Computer-Vision) Based Method 5
2.3 Machine Learning Based Method 6
2.4 Hybrid Method 7
Chapter 3 Preliminary 9
3.1 Color Segmentation 9
3.2 Connected Component Labeling (CCL) 13
3.2.1 Traditional Two-Pass Algorithm 14
3.2.2 Single-Pass Algorithm 15
3.3 Histogram of Oriented Gradient Descriptor (HOG) 21
3.4 Support Vector Machine Classification (SVM) 24
Chapter 4 Proposed method 26
4.1 Detection Procedure 27
4.1.1 Reducing the Searching Space 27
4.1.2 Improved Color Segmentation 28
4.1.3 Single-Pass Connected Component Labeling 29
4.2 Recognition Procedure 30
4.2.1 Preparing the ROIs 30
4.2.2 Simplification of HOG Calculation 30
4.2.3 SVM Classification 32
4.3 Performance Evaluation 33
4.3.1 Testing Dataset and Environment Settings 33
4.3.2 The Influence of Color Segmentation Thresholds 35
4.3.3 The Influence of Reducing HOG Calculation Bits 37
4.3.4 Time Consumption of Software Implementation 40
Chapter 5 Hardware Implementation 41
5.1 Overall Processing Flow 41
5.2 TSR Top Module 43
5.3 Detection Module 44
5.3.1 NRB Transform Module 46
5.3.2 Connected Component Labeling Module 47
5.4 Recognition Module 55
5.4.1 Histogram of Gradient Module 56
5.4.2 Specification and Cycles for Recognition Module 59
5.5 Timing and Speed of Hardware Implementation 61
5.6 Implementation Result 62
5.7 Comparison with Other Works 63
5.7.1 Comparison of CCL Hardware Implementation 63
5.7.2 Comparison of TSR Hardware Implementation 67
Chapter 6 Conclusions and Future Work 69
6.1 Conclusions 69
6.2 Future Work 70
Bibliography 71
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