(3.235.108.188) 您好!臺灣時間:2021/02/26 18:59
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:莊喬丰
研究生(外文):CHUANG, CHIAO-FENG
論文名稱:不同主動區面積與不同鰭數目對Tri-Gate FinFET元件之電性分析及可靠度研究
論文名稱(外文):The Impact of Various Active Surface Area(SA) and Fin Number on Device Performance and Reliability of Tri-Gate FinFET
指導教授:葉文冠葉文冠引用關係
指導教授(外文):YEH, WEN-KUAN
口試委員:楊宜霖張文騰
口試委員(外文):YANG, YI-LINCHANG, WEN-TENG
口試日期:2018-03-22
學位類別:碩士
校院名稱:國立高雄大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:74
中文關鍵詞:鰭式場效電晶體淺溝槽隔離主動區面積接觸蝕刻停止層
外文關鍵詞:FinFETSTIActive Surface AreaContact Etch Stop Layer
相關次數:
  • 被引用被引用:7
  • 點閱點閱:296
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:39
  • 收藏至我的研究室書目清單書目收藏:0
為了達到更佳的性能及可靠度,元件材料及結構不斷地被改良,鰭式場效電晶體憑藉著其優異的元件特性與持續微縮的可行性,取代了傳統的平面場效電晶體。本論文中我們針對通道長度為16nm,寬度為10nm的三閘極鰭式場效電晶體進行研究。
當元件結構由傳統平面轉為立體結構,可能出現不同於以往的現象。在平面場效電晶體中,主動區面積大小對元件的影響,主要來自於製造過程中,淺溝槽內之填充物因溫度而造成的體積變化,進而對元件通道造成擠壓的應力。我們認為在鰭式場效電晶體中,由於通道位置處於淺溝槽隔離的上方,故主動區面積對元件的影響將由其他的物理機制所主導。我們發現當元件上方覆蓋了具拉伸應力之接觸蝕刻停止層後,主動區面積越大之元件使鰭部分產生越嚴重的彎曲現象,通道內感受到越大的擠壓應力,使n型元件電流越小,但可靠度較佳,p型則反之。
我們也探討了單鰭與多鰭結構對三閘極鰭式場效電晶體之影響。由於通道耦合效應與接觸蝕刻停止層造成的通道彎曲效應交互作用,故在多鰭結構下,n型元件歸一化後之電流略小,但可靠度越佳;p型元件鰭數與電流關係則較為複雜,但鰭數越多之元件有越差的可靠度。

To enhance electrical characteristics and reliability, material and structure of device are continuously innovate---Traditional planar MOSFET is replaced by 3D FinFET due to its performance and as well as the capability of scaling. In this work, Tri-Gate FinFETs with 16nm channel length and 10nm fin width are investigated.
Some different phenomena may occur when device structure is transformed from planar MOSFET to 3D FinFET. The influence of the Active Surface Area on the device for the former is derived from the variation of STI oxide volume during the manufacturing process, which causes compressive stress on the channel. Of which the latter is dominated by other physical mechanism due to the fact that the channel is located above STI. Also, it is found that covered by Contact Etch Stop Layer(CESL) with tensile stress, the larger Active Surface Area FinFET has, the more fin bends, resulting in stronger compressive stress onto the channel, which makes Id of nFinFET drop, but with better HCI reliability. pFinFET is the reverse.
We also investigated the impact of single and multi-fin structure in FinFET. The interaction between coupling effect and the fin bending (compressive stress caused by tensile CESL) affects the behavior of FinFET. In consequence, multi-fin structured nFinFET provides slightly lower Id, but better HCI reliability, whereas a pFinFET shows slightly complex relationship between Id and fin number structure and worse HCI reliability as the number of fins increases.

摘要 3
Abstract 5
誌謝 7
目錄 9
圖目錄 11
第一章 緒論 14
1.1 研究背景與動機 14
1.2 文獻探討 16
1.3 論文架構 17
第二章 基礎理論與實驗方法 19
2.1 先進元件製程 19
2.2 應變矽技術 19
2.3 元件可靠度量測理論 21
2.3.1 熱載子效應(Hot Carrier Effect, HCE) 22
2.4 實驗儀器之介紹 22
2.5 元件基本電性量測 23
2.6 元件電性參數分析 23
2.6.1 ID-VG特性曲線 23
2.6.2 ID-VD特性曲線 24
2.6.3 臨界電壓(VTH) 25
2.6.4 轉移電導(GM) 25
2.6.5 次臨界擺幅(S.S.) 25
2.6.6 飽和電流(ID,sat) 26
第三章 不同主動區面積(SA)對元件特性及可靠度之影響 27
3.1 不同主動區面積(SA)之元件基本電性實驗 27
3.1.1 實驗設計 27
3.1.2 基本電性分析 27
3.2 不同主動區面積(SA)之元件HCI可靠度實驗 30
3.2.1 實驗設計 30
3.2.2 可靠度實驗結果分析 31
第四章 不同鰭數對元件特性及可靠度之影響 34
4.1 不同鰭數之元件基本電性實驗 34
4.1.1 實驗設計 34
4.1.2 基本電性分析 34
4.2 不同鰭數之元件HCI可靠度分析 36
4.2.1 實驗設計 37
4.2.2 可靠度實驗結果分析 37
第五章 結論與未來展望 41
5.1 結論 41
5.2 未來展望 42
參考文獻 71


[1]劉傳璽、陳進來,2013,半導體元件物理與製:程理論與實務,台北市:五南圖書出版股份有限公司
[2]葉文冠、陳柏穎、翁俊仁,2011,積體電路製程技術與品質管理,台北市:臺灣東華書局股份有限公司
[3]陳詩堯、民105,不同金屬閘極對多重鰭數N型鰭式場效電晶體之可靠度研究,國立高雄大學電機工程研究所碩士論文
[4]鄭旭廷、民104,多重鰭數對P型鰭式場效電晶體之電性分析及可靠度研究,國立高雄大學電機工程研究所碩士論文
[5]戴安妮、民106,多重鰭數對P型鰭式場效電晶體之電性及可靠度研究,國立高雄大學電機工程研究所碩士論文
[6]洪勤凱、民98,佈局參數效應及淺溝槽絕緣製程對奈米尺寸N型金氧半場效電晶體特性之研究,國立成功大學電機系微電子工程研究所碩士論文
[7]高偉傑、民103,CESL應力層與側壁結構對NMOSFET之應力模擬,國立臺灣師範大學機電科技學系碩士論文
[8]王柏清、吳三連、張守進,接觸孔蝕刻停止層之伸張應力對nMOSFET特性探討,真空科技
[9]Tetsuro Hayashida, Kazuhiko Endo, Yongxun Liu, Shin-Ichi O'uchi, Takashi Matsukawa, Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Hiroki Hashiguchi, Daisuke Kosemura, Takahiro Kamei, Junichi Tsukada; Yuki Ishikawa, Hiromi Yamauchi, Atsushi Ogura, Meishoku Masahara, “Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance”, IEEE Transactions on Electron Devices, Vol. 59, pp. 647-653, 2012.
[10]Moonju Cho, Philippe Roussel, Ben Kaczer, Robin Degraeve, Jacopo Franco, Marc Aoulaiche, Thomas Chiarella, Thomas Kauerauf, Naoto Horiguchi, and Guido Groeseneken, “Channel Hot Carrier Degradation Mechanism in Long/Short Channel n-FinFETs”, IEEE Transactions on Electron Devices, vol. 60, pp. 4002-4007, 2013.
[11]Cheng-Li Lin, Po-Hsiu Hsiao, Wen-Kuan Yeh, Han-Wen Liu, Syuan-Ren Yang, Yu-Ting Chen, Kun-Ming Chen, Wen-Shiang Liao, “Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs”, IEEE Transactions on Electron Devices, vol. 60, pp.3639-3644, 2013.
[12]Sulagna Chatterjee, Sanatan Chattopadhyay, Anirban Bhattacharyya, “Process-induced strain engineering in the silicon-on-sapphire (SOS) fin field effect transistor (FinFET) channels”, International Conference on Computers and Devices for Communication, pp. 1-4, 2015.
[13]Xia Fang, Lingling Sun, Jun Liu, Huang Wang, “A study of the effect of shallow trench isolation technology on MOSFET DC characteristic”, International Symposium on Integrated Circuits, pp. 520-523, 2011.
[14]Francesco Conzatti, Nicola Serra, David Esseni, Marco De Michielis, Alan Paussa, Pierpaolo Palestri, Luca Selmi, Stephen M. Thomas, Terence E. Whall, David Leadley, E. H. C. Parker, Liesbeth Witters, Martin J. Hytch, Etienne Snoeck, T. J. Wang, W. C. Lee, Gerben Doornbos, Georgios Vellianitis, Mark J. H. van Dal, R. J. P. Lander, “Investigation of Strain Engineering in FinFETs Comprising Experimental Analysis and Numerical Simulations”, vol. 58, pp. 1583-1593, 2011.
[15]J. R. Shih, J. J. Wang, W. Ken, Yeng Peng, J. T. Yue, “The study of compressive and tensile stress on MOSFET's I-V, C-V characteristics and it's impacts on hot carrier injection and negative bias temperature instability”, IEEE International Reliability Physics Symposium Proceedings, pp. 612-613, 2003.
[16]S. Zaouia, S. Cristoloveanu, A.H. Perera, “Investigation Of Compressive Strain Effects Induced By STI And ESL”, Nanoscaled Semiconductor-on-Insulator Structures and Devicesm, pp. 239-250, 2007.
[17]T. -Y. Liow, K. -M. Tan, R. Lee, A. Du, C. -H. Tung, G. Samudra, W. -J. Yoo, N. Balasubramanian, Y. -C. Yeo, “Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement”, Symposium on VLSI Technology, pp. 56-57, 2006.
[18]Mu-Chun Wang, Hsin-Chia Yang, Wen-Shiang Liao, Hsiu-Yen Yang, Yao-Yuan Hoe, Kuang-Hung Lin, Shuang-Yuan Chen, “CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication”, International Symposium on Next Generation Electronics, pp. 17-20, 2010.
[19]In-Shik Han, Hee-Hwan Ji, Ook-Sang You, Won-Ho Choi, Jung-Eun Lim, Kyong-Jin Hwang, Sung-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Hi-Deok Lee, “IEEE Transactions on Electron Devices, vol. 55, pp. 1352-1358, 2008.
[20]T. Irisawa, T. Numata, E. Toyoda, N. Hirashita, T. Tezuka, N. Sugiyama, S. Takagi, “Physical Understanding of Strain Effects on Gate Oxide Reliability of MOSFETs”, IEEE Symposium on VLSI Technology, pp. 36-37, 2007.
[21]Cheng Li, Hai Zhao, Gang Mao, “Fin bending mechanism investigation for 14nm FinFET technology”, China Semiconductor Technology International Conference, pp. 1-3, 2017.
[22]Alp H. Gencer, Dimitrios Tsamados, Victor Moroz, “Fin bending due to stress and its simulation”, International Conference on Simulation of Semiconductor Processes and Devices, pp. 109-112, 2013.
[23]Claude Ortolland, Yasutoshi Okuno, Peter Verheyen, Christoph Kerner, Chris Stapelmann, Marc Aoulaiche, Naoto Horiguchi, Thomas Hoffmann, “Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process”, IEEE Transactions on Electron Devices, vol. 56, pp. 1690-1697, 2009.
[24]Yi-Lin Yang, Wenqi Zhang, Tzu-Sung Yen, Jia-Jian Hong, Jie-Chen Wong, Chao-Chen Ku, Tai-Hsuan Wu, Tzuo-Li Wang, Chien-Yi Li, Bing-Tze Wu, Shih-Hung Lin, and Wen-Kuan Yeh, “Examination of hot-carrier stress induced degradation on fin field-effect transistor” Applied Physics Letters, vol.104, No. 8, pp. 083505-1 - 083505-3, 2014.
[25]J.H Han, Choong-Ho Lee, Choong-Ho Lee, Yang-Kyu Choi, “A Comprehensive Study of Hot-Carrier Effects in Body-Tied FinFETs”, Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, pp. 876 - 877, 2005.
[26]E. Takeda, N. Suzuki, “Examination of hot-carrier stress induced degradation on fin field-effect transistor”, IEEE Electron Device Letters, vol.4, No. 4, pp. 111 - 113, 1983.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔