為了達到更佳的性能及可靠度，元件材料及結構不斷地被改良，鰭式場效電晶體憑藉著其優異的元件特性與持續微縮的可行性，取代了傳統的平面場效電晶體。本論文中我們針對通道長度為16nm，寬度為10nm的三閘極鰭式場效電晶體進行研究。
當元件結構由傳統平面轉為立體結構，可能出現不同於以往的現象。在平面場效電晶體中，主動區面積大小對元件的影響，主要來自於製造過程中，淺溝槽內之填充物因溫度而造成的體積變化，進而對元件通道造成擠壓的應力。我們認為在鰭式場效電晶體中，由於通道位置處於淺溝槽隔離的上方，故主動區面積對元件的影響將由其他的物理機制所主導。我們發現當元件上方覆蓋了具拉伸應力之接觸蝕刻停止層後，主動區面積越大之元件使鰭部分產生越嚴重的彎曲現象，通道內感受到越大的擠壓應力，使n型元件電流越小，但可靠度較佳，p型則反之。
我們也探討了單鰭與多鰭結構對三閘極鰭式場效電晶體之影響。由於通道耦合效應與接觸蝕刻停止層造成的通道彎曲效應交互作用，故在多鰭結構下，n型元件歸一化後之電流略小，但可靠度越佳；p型元件鰭數與電流關係則較為複雜，但鰭數越多之元件有越差的可靠度。

To enhance electrical characteristics and reliability, material and structure of device are continuously innovate---Traditional planar MOSFET is replaced by 3D FinFET due to its performance and as well as the capability of scaling. In this work, Tri-Gate FinFETs with 16nm channel length and 10nm fin width are investigated.
Some different phenomena may occur when device structure is transformed from planar MOSFET to 3D FinFET. The influence of the Active Surface Area on the device for the former is derived from the variation of STI oxide volume during the manufacturing process, which causes compressive stress on the channel. Of which the latter is dominated by other physical mechanism due to the fact that the channel is located above STI. Also, it is found that covered by Contact Etch Stop Layer(CESL) with tensile stress, the larger Active Surface Area FinFET has, the more fin bends, resulting in stronger compressive stress onto the channel, which makes Id of nFinFET drop, but with better HCI reliability. pFinFET is the reverse.
We also investigated the impact of single and multi-fin structure in FinFET. The interaction between coupling effect and the fin bending (compressive stress caused by tensile CESL) affects the behavior of FinFET. In consequence, multi-fin structured nFinFET provides slightly lower Id, but better HCI reliability, whereas a pFinFET shows slightly complex relationship between Id and fin number structure and worse HCI reliability as the number of fins increases.

摘要 3
Abstract 5
誌謝 7
目錄 9
圖目錄 11
第一章 緒論 14
1.1 研究背景與動機 14
1.2 文獻探討 16
1.3 論文架構 17
第二章 基礎理論與實驗方法 19
2.1 先進元件製程 19
2.2 應變矽技術 19
2.3 元件可靠度量測理論 21
2.3.1 熱載子效應(Hot Carrier Effect, HCE) 22
2.4 實驗儀器之介紹 22
2.5 元件基本電性量測 23
2.6 元件電性參數分析 23
2.6.1 ID-VG特性曲線 23
2.6.2 ID-VD特性曲線 24
2.6.3 臨界電壓(VTH) 25
2.6.4 轉移電導(GM) 25
2.6.5 次臨界擺幅(S.S.) 25
2.6.6 飽和電流(ID,sat) 26
第三章 不同主動區面積(SA)對元件特性及可靠度之影響 27
3.1 不同主動區面積(SA)之元件基本電性實驗 27
3.1.1 實驗設計 27
3.1.2 基本電性分析 27
3.2 不同主動區面積(SA)之元件HCI可靠度實驗 30
3.2.1 實驗設計 30
3.2.2 可靠度實驗結果分析 31
第四章 不同鰭數對元件特性及可靠度之影響 34
4.1 不同鰭數之元件基本電性實驗 34
4.1.1 實驗設計 34
4.1.2 基本電性分析 34
4.2 不同鰭數之元件HCI可靠度分析 36
4.2.1 實驗設計 37
4.2.2 可靠度實驗結果分析 37
第五章 結論與未來展望 41
5.1 結論 41
5.2 未來展望 42
參考文獻 71

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