臺灣博碩士論文加值系統

本篇論文提出基於標準元件庫設計流程來設計具有修正工作週期校正之功能的全數位延遲鎖定迴路。該電路採用兩組半延遲線的架構來實現工作週期校正，在完成週期擷取後，透過半延遲線的延遲量會等於輸入時脈週期一半的特性，合成出工作週期為50%的輸出時脈。而半延遲線採用粗調延遲線與細調延遲線串接的方式來達到更高的解析度。除此之外，文中提出一種多相位循環式時間至數位轉換器，透過振盪器產生不同相位的時脈結合計數器產生控制碼。並搭配漸進比較搜尋控制機制來達到誤差修正及快速鎖定之功能。

本論文電路以晶片中心提供的UMC製程與標準元件庫進行設計與實現，後模擬結果可得到輸入時脈的操作頻率為90 ~ 600MHz；可容忍輸入時脈的工作週期為20% ~ 70%；時脈誤差校正可達-31.88ps ~ +6.01ps；輸出時脈工作週期誤差量為49.64% ~ 52.23%；需要的鎖定時間少於40個週期。另外本電路完成鎖定後，會進入閉迴路控制模式。當輸入時脈延遲發生變化時，可透過計數器使輸出時脈重新校正。

In this thesis, an all-digital delay-locked loop with duty-cycle correction is proposed and implemented with the cell-based design flow. The proposed circuit utilizes the two half-delay line architecture to realize the function of duty cycle correction. After the period acquisition is done, the delay time of the half-delay line is set to be equal to one half of the input clock period, and the duty cycle of the output clock is synthesized to be 50%. The half-delay line comprises a coarse delay line and a fine delay line connected in series so as to obtain higher resolution. In addition, a multi-phase cyclic time-to-digital converter is presented here to generate the control codes with the aid of the oscillator outputs with different phases. And the successive approximation register control mechanism also assists in reducing the phase error to achieve fast-locking capability.

A test chip is designed and simulated in UMC CMOS 0.18μm process. The circuit can operate at the input clock frequency from 90 ~ 600 MHz with the duty cycle range of 20% ~ 70%, and the skew is reduced to be within -31.88ps ~ +6.01ps. The deviation of the output duty cycle is within 49.64% ~ 52.23%. The required lock time is less than 40 cycles. The proposed circuit will enter the closed-loop control mode after locking. The output clock can be re-calibrated via the counter if the delay of the input clock is changed.

摘要
ABSTRACT
目錄
表目錄
圖目錄
第一章 緒論
1.1 研究動機
1.2 電路設計流程
1.2.1 全客戶式設計流程
1.2.2 基於標準元件庫設計流程
1.3 論文架構
第二章 延遲鎖定迴路及工作週期修正電路簡介
2.1 類比式延遲鎖定迴路
2.2 數位式延遲鎖定迴路
2.2.1 移位暫存器式
2.2.2 計數器式
2.2.3 漸進比較式
2.2.4 時間至數位轉換式
2.3 工作週期修正電路
2.3.1 類比式
2.3.2 數位式
第三章 以標準元件庫建構具有週期修正功能之全數位延遲鎖定迴路
3.1 架構介紹
3.2 操作原理
3.3 電路設計
3.3.1 數位控制延遲線
3.3.2 多相位循環式時間至數位轉換器
3.3.3 邊緣合成器
3.3.4 相位偵測器
3.3.5 除頻器
3.3.6 混合式漸進比較搜尋控制器
3.3.7 狀態控制器
第四章 電路設計與模擬
4.1 設計流程
4.2 實體電路佈局圖與規格表
4.3 後模擬結果
4.3.1 數位控制延遲線特性
4.3.2 整體系統操作模擬
4.4 電路規格與比較表
4.5 量測環境與考量
第五章 總結
5.1 結論
5.2 未來展望
參考文獻

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