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研究生:蘇泓元
研究生(外文):Hung-Yuan Su
論文名稱:以機器學習技術輔助之快速電源一致性檢測
論文名稱(外文):A Learning-Based SPICE Simulation Framework for Fast Power Integrity Check
指導教授:陳勇志陳勇志引用關係
指導教授(外文):Yung-Chih Chen
口試委員:曾王道劉一宇
口試委員(外文):Wang-Dauh TsengYi-Yu Liu
口試日期:2018-07-25
學位類別:碩士
校院名稱:元智大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2018
畢業學年度:106
語文別:中文
論文頁數:58
中文關鍵詞:機器學習電源一致性
外文關鍵詞:machine learningpower integrityTensroFlowHSPICE
相關次數:
  • 被引用被引用:0
  • 點閱點閱:174
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  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
隨著半導體製程的進步,電晶體的製造大小不斷微縮,同時金屬導線也變得越來越細,使得導線所造成的電壓下降量增加,就有可能會影響到電路的延遲甚至是功能的正確性。因此,為了避免電路元件供電電壓不足的問題,檢查電源一致性在先進製程中就成了非常重要的環節。在本篇論文中,我們提出一個採用機器學習的技術來輔助,以HSPICE作為模擬分析引擎的解決方案。藉由抽取電路中重要的資訊,我們能夠在晶片設計流程完成元件擺放與供電網路建構後,快速地得到電路的供電資訊。實驗結果顯示,雖然模擬結果與商業工具相比,在準確度上有所犧牲,但能夠在較短的時間內得到模擬的結果。模擬的電壓值與商業工具的數值,其相關係數能達到0.99以上。在完整的晶片模擬上,提出的解決方案大約能減少40.84%的執行時間。如果進一步使用機器學習技術輔助,挑選出晶片上電壓下降的嚴重區域,則我們提出的解決方案能夠省下大約67.56%的執行時間。
As semiconductor processing technology advances, transistor and interconnect feature sizes are continually shrinking for high-level integration. The side effect results in increasing effective voltage drop on the metal wires. The voltage drop effect would lead to circuit delay variation and even result in circuit malfunctioning. In order to avoid the effective voltage drop issues in advanced process, checking power integrity becomes an important step in IC design flow. In this thesis, we propose a framework for checking power integrity by using HSPICE simulation with machine learning techniques. The main idea of the framework is to extract the essential data from the circuit, so that we could obtain the power supply information fast when the cell placement and the power delivery network construction are completed. Experimental results shows that though there is accuracy loss between our simulation results and the results obtained from commercial tools, the runtime of the proposed framework is smaller than the commercial tools. The correlation coefficient between our framework and commercial tool is over 0.99. In a full chip simulation, the proposed framework can reduce the total execution time by 40.84%. Furthermore, with the support of machine learning techniques for voltage drop hotspot blocks selection, our proposed framework could save the total execution time up to 67.56%.
摘 要.....................................................i
ABSTRACT.................................................ii
誌 謝...................................................iii
目 錄....................................................iv
表 目 錄..................................................vi
圖 目 錄.................................................vii
第一章、研究簡介............................................1
1.1. Power Integrity......................................1
1.2. Effective Voltage Drop...............................2
1.3. PDN - Power Delivery Network ........................2
1.4. Machine Learning ....................................3
第二章、文獻探討............................................4
2.1. IC Design Flow Consider Power Integrity & PDN Construction..............................................4
2.2. Voltage Drop Prediction by Machine Learning..........6
第三章、研究問題............................................7
3.1. 研究動機..............................................7
3.2. Problem Formulation .................................7
第四章、研究方法...........................................10
4.1. Framework Overview .................................10
4.2. TensorFlow..........................................13
4.2.1. Introduction of TensorFlow........................13
4.2.2. TensorFlow APIs...................................14
4.2.3. Training、Evaluation以及Prediction ................15
4.3. HSPICE..............................................23
4.3.1. Introduction of SPICE Simulation .................23
4.3.2. 建立Equivalent Circuit ...........................24
4.3.3. Metal-1 Standard Cell Row Block ..................24
4.3.4. Stacked VIA.......................................28
4.3.5. High Level PDN Block .............................29
4.3.6. HSPICE Simulation ................................30
4.3.7. 加速模擬的選項.....................................30
第五章、實作與實驗結果.....................................33
5.1. 實驗環境.............................................33
5.2. 實驗數據.............................................35
5.2.1. HSPICE的Accuracy與時間比較.........................35
5.2.2. HSPICE模擬啟用Merge Function加速...................41
5.2.3. TensorFlow Prediction執行時間與效度分析.............47
5.2.4. Framework的Accuracy與執行時間比較..................50
第六章、結論..............................................55
參考文獻..................................................57
[1] Gordon E. Moore, Cramming More Components Onto Integrated Circuits, Proc. IEEE. 1998. pp. 82–85. doi:10.1109/JPROC.1998.658762.
[2] S.-W. Wu, Y.-W. Chang, Efficient Power/Ground Network Analysis for Power Integrity-driven Design Methodology, in: Proc. 41st Des. Autom. Conference, 2004. pp. 177–180. doi:10.1145/996566.996617.
[3] I. M. Liu, H. M. Chen, T. L. Chou, Aziz, A., and Wong, D. F., Integrated Power Supply Planning and Floorplanning, in: Proc. ASP-DAC, 2001. pp. 589-594. doi: 10.1109/ASPDAC.2001.913372.
[4] Y.L. Chuang, P.W. Lee, Y.W. Chang, Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs, IEEE Trans. Computer-Aided Design Integrated Circuits and System, 2011. pp. 1649–1662. doi:10.1109/TCAD.2011.2163071.
[5] A. B. Kahng, B. Liu, and Q. Wang, Supply Voltage Degradation Aware Analytical Placement, in: Proc. ACM/IEEE Int. Conf. Comput. Des.,2005, pp. 437–443. doi: 10.1109/ICCD.2005.101.
[6] W.H. Chang, M.C.T. Chao, S.H. Chen, Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer, IEEE Trans. Very Large Scale Integr. VLSI Syst., 2014. pp. 1069–1081. doi:10.1109/TVLSI.2013.2264686.
[7] W-H. Chang, C-H. Lin, S-P. Mu, L-D. Chen, C-H. Tsai, Y-C. Chiu, M. C-T. Chao, Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017. pp. 1237-1250. doi: 10.1109/TCAD.2017.2648842.
[8] T.W. Tseng, C.T. Lin, C.H. Lee, Y.F. Chou, D.M. Kwai, A Power Delivery Network (PDN) Engineering Change Order (ECO) Approach for Repairing IR-drop Failures after the Routing Stage, in: Tech. Pap. 2014 Int. Symp. VLSI Des. Autom. Test, 2014. pp. 1–4. doi:10.1109/VLSI-DAT.2014.6834874.
[9] F. Ye, F. Firouzi, Y. Yang, K. Chakrabarty, M. B. Tahoori, On-Chip Voltage-Droop Prediction Using Support-Vector Machines, in: Proc. IEEE VLSI Test Symp. (VTS), 2014. pp. 1-6. doi: 10.1109/VTS.2014.6818798.
[10] Synopsys PrimeRail, http://www.synopsys.com/implementation-and-signoff/signoff/primerail.html (accessed June 07, 2018).
[11] Apache Design, Inc. RedHawk, http://www.apache-da.com/products/redhawk (accessed June 07, 2018).
[12] Synopsys HSPICE, https://www.synopsys.com/verification/ams-verification/circuit-simulation/hspice.html (accessed June 07, 2018).
[13] TensorFlow, https://www.tensorflow.org (accessed June 07, 2018).
[14] Synopsys SAED 32nm Generic Libraries & iPDK, https://www.synopsys.com/community/university-program/teaching-resources.html (accessed October 10, 2017).
[15] David Lundgren, double_fpu_verilog :: Overview :: OpenCores, https://opencores.org/project,double_fpu (accessed June 20, 2014).
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