臺灣博碩士論文加值系統

降低操作電壓以達到節能的目標已經是熟知之設計技術，目前也有大量文獻探討動態追蹤最低操作電壓並防止或補救過度降壓造成之計算錯誤。本研究主要是以 FPGA 建構動態調整電壓之設計平台，以期在實體晶片未完成前，評估具錯誤容忍能力之深度神經網路在過度降壓時之系統行為。我們以哈佛大學在 2017 年國際固態電子電路會議發表之神經網路架構作為參考設計，發現極小量時序錯誤 (timing error) 即會造成該設計極大之計算誤差 (arithmetic error)，阻止進一步降壓節能。我們利用 ReLU 非負數計算的特性，提出以無號計算為基礎之更新架構，在同樣之精準度條件下可以進一步壓低 40mV 操作電壓，降低約 10% 能源消耗。

The goal of reducing operating voltage to achieve energy savings is well known design technology, and there is much literature on dynamically tracking the minimum operating voltage and preventing or remedying the computational errors caused by voltage-over-scaled. This research is mainly based on the FPGA to construct a dynamic voltage scaling design platform, in order to evaluate the system behavior of the deep neural network with fault tolerance during voltage-over-scaled before the physical chip is completed. Using the neural network architecture published by Harvard University at the International Solid-State Circuits Conference in 2017 as a reference design, we found that a very small amount of timing error would cause a great arithmetic error in the design, preventing further voltage reduction and energy saving. Using the characteristics of ReLU non-negative calculations, we propose an update architecture based on the unsigned calculation, which can further reduce the operating voltage of 40mV and reduce energy consumption by about 10% under the same precision conditions.

誌謝 i
摘要 ii
目錄 v
圖目錄 vii
表目錄 ix
第一章 序論 1
1.1研究背景 1
1.2研究動機 4
1.3研究貢獻 5
1.4論文架構 6
第二章 背景 7
2.1手寫數字辨識系統 8
2.2時序餘裕偵測器 11
第三章 過度降壓神經網路實現 16
3.1乘法器動態延遲量測 17
3.2可量化神經網路錯誤容忍度平台 19
3.3可擷取神經網路計算誤差平台 26
3.4過度降壓神經網路驗證平台 30
第四章 過度降壓神經網路效能評估 34
4.1神經網路效能量測 35
4.2過度降壓神經網路成效分析 38
第五章 結論 43
參考文獻 44

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